| V1 |
smoke |
keymgr_dpe_smoke |
12.870s |
2.252ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
keymgr_dpe_csr_hw_reset |
1.840s |
46.884us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
keymgr_dpe_csr_rw |
2.020s |
24.188us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
keymgr_dpe_csr_bit_bash |
8.730s |
673.769us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
keymgr_dpe_csr_aliasing |
5.620s |
635.281us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
keymgr_dpe_csr_mem_rw_with_rand_reset |
1.920s |
14.928us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
keymgr_dpe_csr_rw |
2.020s |
24.188us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
5.620s |
635.281us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
intr_test |
keymgr_dpe_intr_test |
1.700s |
35.151us |
1 |
1 |
100.00 |
| V2 |
alert_test |
keymgr_dpe_alert_test |
1.740s |
37.195us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
keymgr_dpe_tl_errors |
3.320s |
101.768us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
keymgr_dpe_tl_errors |
3.320s |
101.768us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
keymgr_dpe_csr_hw_reset |
1.840s |
46.884us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
2.020s |
24.188us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
5.620s |
635.281us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
2.750s |
124.525us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
keymgr_dpe_csr_hw_reset |
1.840s |
46.884us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
2.020s |
24.188us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
5.620s |
635.281us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
2.750s |
124.525us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
4 |
4 |
100.00 |
| V2S |
tl_intg_err |
keymgr_dpe_sec_cm |
14.080s |
2.469ms |
1 |
1 |
100.00 |
|
|
keymgr_dpe_tl_intg_err |
7.520s |
283.900us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error |
keymgr_dpe_shadow_reg_errors |
2.420s |
74.181us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
keymgr_dpe_shadow_reg_errors |
2.420s |
74.181us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
keymgr_dpe_shadow_reg_errors |
2.420s |
74.181us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
keymgr_dpe_shadow_reg_errors |
2.420s |
74.181us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
keymgr_dpe_shadow_reg_errors_with_csr_rw |
4.600s |
207.574us |
1 |
1 |
100.00 |
| V2S |
prim_count_check |
keymgr_dpe_sec_cm |
14.080s |
2.469ms |
1 |
1 |
100.00 |
| V2S |
prim_fsm_check |
keymgr_dpe_sec_cm |
14.080s |
2.469ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
4 |
4 |
100.00 |
|
|
TOTAL |
|
|
14 |
14 |
100.00 |