KMAC/MASKED Simulation Results

Tuesday June 17 2025 17:02:32 UTC

GitHub Revision: b69339b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	11.480s	1.672ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.640s	61.004us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.870s	98.447us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.410s	6.041ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.080s	145.070us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.700s	271.320us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.870s	98.447us	1	1	100.00
		kmac_csr_aliasing	6.080s	145.070us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.610s	11.956us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.840s	173.794us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	8.913m	27.339ms	1	1	100.00
V2	burst_write	kmac_burst_write	7.564m	10.640ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	23.527m	18.814ms	1	1	100.00
		kmac_test_vectors_sha3_256	21.263m	46.175ms	1	1	100.00
		kmac_test_vectors_sha3_384	24.515m	84.865ms	1	1	100.00
		kmac_test_vectors_sha3_512	16.270s	3.478ms	1	1	100.00
		kmac_test_vectors_shake_128	36.041m	370.851ms	1	1	100.00
		kmac_test_vectors_shake_256	1.701m	7.401ms	1	1	100.00
		kmac_test_vectors_kmac	3.580s	34.574us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.460s	119.134us	1	1	100.00
V2	sideload	kmac_sideload	5.112m	5.219ms	1	1	100.00
V2	app	kmac_app	2.588m	47.917ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.720m	95.076ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.600m	6.007ms	1	1	100.00
V2	error	kmac_error	3.612m	37.051ms	1	1	100.00
V2	key_error	kmac_key_error	9.040s	21.400ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.340s	42.827us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.790s	21.606us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.680s	89.686us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	37.490s	7.260ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.990s	23.837us	1	1	100.00
V2	stress_all	kmac_stress_all	23.201m	53.467ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.650s	75.070us	1	1	100.00
V2	alert_test	kmac_alert_test	1.630s	56.028us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.770s	46.156us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.770s	46.156us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.640s	61.004us	1	1	100.00
		kmac_csr_rw	1.870s	98.447us	1	1	100.00
		kmac_csr_aliasing	6.080s	145.070us	1	1	100.00
		kmac_same_csr_outstanding	3.120s	90.337us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.640s	61.004us	1	1	100.00
		kmac_csr_rw	1.870s	98.447us	1	1	100.00
		kmac_csr_aliasing	6.080s	145.070us	1	1	100.00
		kmac_same_csr_outstanding	3.120s	90.337us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.310s	140.875us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.310s	140.875us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.310s	140.875us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.310s	140.875us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.310s	828.242us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	30.800s	4.836ms	1	1	100.00
		kmac_tl_intg_err	3.000s	437.882us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.000s	437.882us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.990s	23.837us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	11.480s	1.672ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	5.112m	5.219ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.310s	140.875us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	30.800s	4.836ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	30.800s	4.836ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	30.800s	4.836ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	11.480s	1.672ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.990s	23.837us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	30.800s	4.836ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.540m	39.040ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	11.480s	1.672ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.550s	308.682us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.42002065389776224261766221299752306133041695967681610577226019221905935782380
      Line 80, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 308682058 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 308682058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---