KMAC/UNMASKED Simulation Results

Tuesday June 17 2025 17:02:32 UTC

GitHub Revision: b69339b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	9.260s	1.360ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.630s	48.345us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.770s	17.825us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.230s	5.233ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.580s	773.378us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.120s	26.260us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.770s	17.825us	1	1	100.00
		kmac_csr_aliasing	4.580s	773.378us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.600s	21.510us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.010s	37.264us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	26.323m	385.977ms	1	1	100.00
V2	burst_write	kmac_burst_write	2.988m	3.090ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	27.447m	169.644ms	1	1	100.00
		kmac_test_vectors_sha3_256	26.690s	4.228ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.785m	167.618ms	1	1	100.00
		kmac_test_vectors_sha3_512	11.510s	5.201ms	1	1	100.00
		kmac_test_vectors_shake_128	27.881m	70.820ms	1	1	100.00
		kmac_test_vectors_shake_256	4.108m	64.288ms	1	1	100.00
		kmac_test_vectors_kmac	2.390s	570.194us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.540s	135.841us	1	1	100.00
V2	sideload	kmac_sideload	5.145m	101.950ms	1	1	100.00
V2	app	kmac_app	48.150s	13.897ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.372m	10.659ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.196m	10.056ms	1	1	100.00
V2	error	kmac_error	3.750m	12.186ms	1	1	100.00
V2	key_error	kmac_key_error	4.590s	874.853us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.120s	61.668us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	19.210s	492.975us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	23.860s	468.250us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	14.170s	2.849ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	7.390s	621.873us	1	1	100.00
V2	stress_all	kmac_stress_all	2.346m	7.277ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.530s	13.166us	1	1	100.00
V2	alert_test	kmac_alert_test	1.550s	21.678us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.840s	234.714us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.840s	234.714us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.630s	48.345us	1	1	100.00
		kmac_csr_rw	1.770s	17.825us	1	1	100.00
		kmac_csr_aliasing	4.580s	773.378us	1	1	100.00
		kmac_same_csr_outstanding	2.450s	141.809us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.630s	48.345us	1	1	100.00
		kmac_csr_rw	1.770s	17.825us	1	1	100.00
		kmac_csr_aliasing	4.580s	773.378us	1	1	100.00
		kmac_same_csr_outstanding	2.450s	141.809us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.280s	130.087us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.280s	130.087us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.280s	130.087us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.280s	130.087us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.850s	24.125us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	30.370s	12.493ms	1	1	100.00
		kmac_tl_intg_err	4.020s	385.419us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.020s	385.419us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	7.390s	621.873us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	9.260s	1.360ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	5.145m	101.950ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.280s	130.087us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	30.370s	12.493ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	30.370s	12.493ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	30.370s	12.493ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	9.260s	1.360ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	7.390s	621.873us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	30.370s	12.493ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.179m	24.375ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	9.260s	1.360ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.452m	4.467ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.27794283320448887411206937218328947097428274456683777503481720201231307701484
      Line 292, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4467434027 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 4467434027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.54802777054171848993788762527397741212387034191921966366534064862223244808658
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[42] & 'hffffffff)))'
        UVM_ERROR @  24124894 ps: (kmac_csr_assert_fpv.sv:518) [ASSERT FAILED] prefix_3_rd_A
        UVM_INFO @  24124894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---