b69339b| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 1.117m | 11.072ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 3.000s | 13.909us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 4.000s | 113.519us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 5.000s | 111.571us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 4.000s | 18.265us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 4.000s | 834.669ns | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 4.000s | 113.519us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 4.000s | 18.265us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | mbx_stress | mbx_stress | 35.000s | 6.514ms | 1 | 1 | 100.00 |
| mbx_stress_zero_delays | 1.000m | 2.613ms | 1 | 1 | 100.00 | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 17.000s | 2.094ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 3.000s | 60.812us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 4.000s | 4.374us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 4.000s | 4.374us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 3.000s | 13.909us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 113.519us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 18.265us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 33.840us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 3.000s | 13.909us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 113.519us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 18.265us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 33.840us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 6 | 83.33 | |||
| V2S | tl_intg_err | mbx_sec_cm | 3.000s | 22.003us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 4.000s | 16.788us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| TOTAL | 11 | 14 | 78.57 |
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutFullData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_errors.56621476213849080709613296831521070748948462029111703864226438986517445708298
Line 82, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_ERROR @ 4373894 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xff404cf4 a_data = 0x4ac45d88 a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0xf6 a_opcode = PutFullData a_user = 0x1aaea d_data = 0xffdf33e3 d_size = 0x3 d_param = 0x0 d_source = 0x81 d_opcode = AccessAck d_error = 0 d_user = 10010111011110 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 4373894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Get a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_intg_err.6007251322894399134876412298152600132450378121944394504190009168463525871034
Line 96, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 16788355 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x183e7f75 a_data = 0xea77bc55 a_mask = 0x2 a_size = 0x0 a_param = 0x0 a_source = 0xec a_opcode = Get a_user = 0x27157 d_data = 0xa1c3f5ee d_size = 0x0 d_param = 0x0 d_source = 0x9b d_opcode = AccessAck d_error = 0 d_user = 100111111000 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 16788355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutPartialData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_csr_mem_rw_with_rand_reset.64861512727089422097687571256848576099994723740015079061134814407865204940329
Line 83, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 834669 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xc8485148 a_data = 0xc3cf2508 a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0x6a a_opcode = PutPartialData a_user = 0x1af8e d_data = 0x3d1438b4 d_size = 0x3 d_param = 0x0 d_source = 0x7f d_opcode = AccessAck d_error = 0 d_user = 1010100011101 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 834669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---