OTBN Simulation Results

Tuesday June 17 2025 17:02:32 UTC

GitHub Revision: b69339b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 11.000s 41.818us 1 1 100.00
V1 single_binary otbn_single 10.000s 42.546us 1 1 100.00
V1 csr_hw_reset otbn_csr_hw_reset 8.000s 22.802us 1 1 100.00
V1 csr_rw otbn_csr_rw 5.000s 25.867us 1 1 100.00
V1 csr_bit_bash otbn_csr_bit_bash 8.000s 99.940us 1 1 100.00
V1 csr_aliasing otbn_csr_aliasing 6.000s 52.902us 1 1 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 8.000s 29.876us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 5.000s 25.867us 1 1 100.00
otbn_csr_aliasing 6.000s 52.902us 1 1 100.00
V1 mem_walk otbn_mem_walk 19.000s 360.453us 1 1 100.00
V1 mem_partial_access otbn_mem_partial_access 10.000s 365.760us 1 1 100.00
V1 TOTAL 9 9 100.00
V2 reset_recovery otbn_reset 19.000s 202.907us 1 1 100.00
V2 multi_error otbn_multi_err 1.783m 659.269us 1 1 100.00
V2 back_to_back otbn_multi 21.000s 305.924us 1 1 100.00
V2 stress_all otbn_stress_all 37.000s 126.110us 1 1 100.00
V2 lc_escalation otbn_escalate 8.000s 60.742us 1 1 100.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 13.000s 49.631us 1 1 100.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 38.000s 188.317us 1 1 100.00
V2 alert_test otbn_alert_test 6.000s 35.983us 1 1 100.00
V2 intr_test otbn_intr_test 5.000s 31.635us 1 1 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 8.000s 51.468us 1 1 100.00
V2 tl_d_illegal_access otbn_tl_errors 8.000s 51.468us 1 1 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 8.000s 22.802us 1 1 100.00
otbn_csr_rw 5.000s 25.867us 1 1 100.00
otbn_csr_aliasing 6.000s 52.902us 1 1 100.00
otbn_same_csr_outstanding 6.000s 33.824us 1 1 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 8.000s 22.802us 1 1 100.00
otbn_csr_rw 5.000s 25.867us 1 1 100.00
otbn_csr_aliasing 6.000s 52.902us 1 1 100.00
otbn_same_csr_outstanding 6.000s 33.824us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S mem_integrity otbn_imem_err 10.000s 25.388us 1 1 100.00
otbn_dmem_err 9.000s 66.522us 1 1 100.00
V2S internal_integrity otbn_alu_bignum_mod_err 8.000s 195.292us 1 1 100.00
otbn_controller_ispr_rdata_err 9.000s 202.717us 1 1 100.00
otbn_mac_bignum_acc_err 11.000s 67.109us 1 1 100.00
otbn_urnd_err 8.000s 35.229us 1 1 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 7.000s 19.889us 1 1 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 9.000s 12.660us 1 1 100.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 9.000s 30.127us 1 1 100.00
V2S tl_intg_err otbn_sec_cm 2.983m 4.732ms 1 1 100.00
otbn_tl_intg_err 31.000s 200.698us 1 1 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 26.000s 833.717us 1 1 100.00
V2S prim_fsm_check otbn_sec_cm 2.983m 4.732ms 1 1 100.00
V2S prim_count_check otbn_sec_cm 2.983m 4.732ms 1 1 100.00
V2S sec_cm_mem_scramble otbn_smoke 11.000s 41.818us 1 1 100.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 9.000s 66.522us 1 1 100.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 10.000s 25.388us 1 1 100.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 31.000s 200.698us 1 1 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 8.000s 60.742us 1 1 100.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 10.000s 25.388us 1 1 100.00
otbn_dmem_err 9.000s 66.522us 1 1 100.00
otbn_zero_state_err_urnd 13.000s 49.631us 1 1 100.00
otbn_illegal_mem_acc 7.000s 19.889us 1 1 100.00
otbn_sec_cm 2.983m 4.732ms 1 1 100.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 2.983m 4.732ms 1 1 100.00
V2S sec_cm_scramble_key_sideload otbn_single 10.000s 42.546us 1 1 100.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 10.000s 25.388us 1 1 100.00
otbn_dmem_err 9.000s 66.522us 1 1 100.00
otbn_zero_state_err_urnd 13.000s 49.631us 1 1 100.00
otbn_illegal_mem_acc 7.000s 19.889us 1 1 100.00
otbn_sec_cm 2.983m 4.732ms 1 1 100.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 2.983m 4.732ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 8.000s 60.742us 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 10.000s 25.388us 1 1 100.00
otbn_dmem_err 9.000s 66.522us 1 1 100.00
otbn_zero_state_err_urnd 13.000s 49.631us 1 1 100.00
otbn_illegal_mem_acc 7.000s 19.889us 1 1 100.00
otbn_sec_cm 2.983m 4.732ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 2.983m 4.732ms 1 1 100.00
V2S sec_cm_data_reg_sw_sca otbn_single 10.000s 42.546us 1 1 100.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 9.000s 15.253us 1 1 100.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 8.000s 59.397us 1 1 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 34.000s 710.434us 1 1 100.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 34.000s 710.434us 1 1 100.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 11.000s 26.857us 1 1 100.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 2.983m 4.732ms 1 1 100.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 2.983m 4.732ms 1 1 100.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 10.000s 56.910us 1 1 100.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 2.983m 4.732ms 1 1 100.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 2.983m 4.732ms 1 1 100.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 8.000s 13.858us 1 1 100.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 8.000s 13.858us 1 1 100.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 8.000s 11.700us 1 1 100.00
V2S sec_cm_data_mem_sec_wipe otbn_single 10.000s 42.546us 1 1 100.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 10.000s 42.546us 1 1 100.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 10.000s 42.546us 1 1 100.00
V2S sec_cm_write_mem_integrity otbn_multi 21.000s 305.924us 1 1 100.00
V2S sec_cm_ctrl_flow_count otbn_single 10.000s 42.546us 1 1 100.00
V2S sec_cm_ctrl_flow_sca otbn_single 10.000s 42.546us 1 1 100.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 8.000s 14.418us 1 1 100.00
V2S sec_cm_key_sideload otbn_single 10.000s 42.546us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 2.983m 4.732ms 1 1 100.00
V2S TOTAL 20 20 100.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 1.350m 1.799ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 41 41 100.00