ROM_CTRL/32KB Simulation Results

Tuesday June 17 2025 17:02:32 UTC

GitHub Revision: b69339b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 4.510s 598.368us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 5.100s 133.003us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.150s 295.261us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.420s 169.161us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.310s 384.402us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 5.510s 189.964us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.150s 295.261us 1 1 100.00
rom_ctrl_csr_aliasing 4.310s 384.402us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 5.530s 350.756us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5.020s 1.418ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 4.560s 781.829us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 11.870s 1.725ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 7.720s 2.799ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.460s 128.138us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 10.560s 2.103ms 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 10.560s 2.103ms 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 5.100s 133.003us 1 1 100.00
rom_ctrl_csr_rw 6.150s 295.261us 1 1 100.00
rom_ctrl_csr_aliasing 4.310s 384.402us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.710s 127.180us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 5.100s 133.003us 1 1 100.00
rom_ctrl_csr_rw 6.150s 295.261us 1 1 100.00
rom_ctrl_csr_aliasing 4.310s 384.402us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.710s 127.180us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.215m 5.465ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 15.190s 1.965ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.860m 2.404ms 1 1 100.00
rom_ctrl_tl_intg_err 39.340s 447.628us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.860m 2.404ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.860m 2.404ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.215m 5.465ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.215m 5.465ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.215m 5.465ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.215m 5.465ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.215m 5.465ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.860m 2.404ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.860m 2.404ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 4.510s 598.368us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 4.510s 598.368us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 4.510s 598.368us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 39.340s 447.628us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.215m 5.465ms 1 1 100.00
rom_ctrl_kmac_err_chk 7.720s 2.799ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.215m 5.465ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.215m 5.465ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.215m 5.465ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 15.190s 1.965ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.860m 2.404ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 4.536m 23.599ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00