SPI_HOST Simulation Results

Tuesday June 17 2025 17:02:32 UTC

GitHub Revision: b69339b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	7.000s	168.221us	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	21.050us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	18.361us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	6.000s	216.287us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	61.029us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	95.652us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	18.361us	1	1	100.00
		spi_host_csr_aliasing	4.000s	61.029us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	16.500us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	59.988us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	4.000s	30.015us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	5.000s	38.986us	1	1	100.00
		spi_host_error_cmd	4.000s	30.866us	1	1	100.00
		spi_host_event	12.000s	2.189ms	1	1	100.00
V2	clock_rate	spi_host_speed	4.000s	57.479us	1	1	100.00
V2	speed	spi_host_speed	4.000s	57.479us	1	1	100.00
V2	chip_select_timing	spi_host_speed	4.000s	57.479us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	6.000s	85.257us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	66.976us	1	1	100.00
V2	cpol_cpha	spi_host_speed	4.000s	57.479us	1	1	100.00
V2	full_cycle	spi_host_speed	4.000s	57.479us	1	1	100.00
V2	duplex	spi_host_smoke	7.000s	168.221us	1	1	100.00
V2	tx_rx_only	spi_host_smoke	7.000s	168.221us	1	1	100.00
V2	stress_all	spi_host_stress_all	21.000s	575.210us	1	1	100.00
V2	spien	spi_host_spien	5.000s	178.983us	1	1	100.00
V2	stall	spi_host_status_stall	16.000s	434.784us	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	4.000s	654.464us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	5.000s	38.986us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	77.964us	1	1	100.00
V2	intr_test	spi_host_intr_test	3.000s	50.377us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	403.696us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	403.696us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	21.050us	1	1	100.00
		spi_host_csr_rw	3.000s	18.361us	1	1	100.00
		spi_host_csr_aliasing	4.000s	61.029us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	57.399us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	21.050us	1	1	100.00
		spi_host_csr_rw	3.000s	18.361us	1	1	100.00
		spi_host_csr_aliasing	4.000s	61.029us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	57.399us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	109.957us	1	1	100.00
		spi_host_sec_cm	3.000s	243.813us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	109.957us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	7.100m	11.441ms	1	1	100.00
		TOTAL			26	26	100.00