UART Simulation Results

Tuesday June 17 2025 17:02:32 UTC

GitHub Revision: b69339b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.290s	518.541us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.730s	22.108us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.750s	34.536us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.220s	1.082ms	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.570s	28.108us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.900s	86.010us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.750s	34.536us	1	1	100.00
		uart_csr_aliasing	1.570s	28.108us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	20.040s	16.470ms	1	1	100.00
V2	parity	uart_smoke	2.290s	518.541us	1	1	100.00
		uart_tx_rx	20.040s	16.470ms	1	1	100.00
V2	parity_error	uart_intr	15.480s	25.874ms	1	1	100.00
		uart_rx_parity_err	11.600s	32.220ms	1	1	100.00
V2	watermark	uart_tx_rx	20.040s	16.470ms	1	1	100.00
		uart_intr	15.480s	25.874ms	1	1	100.00
V2	fifo_full	uart_fifo_full	49.000s	42.090ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	33.740s	30.207ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	15.290s	49.390ms	1	1	100.00
V2	rx_frame_err	uart_intr	15.480s	25.874ms	1	1	100.00
V2	rx_break_err	uart_intr	15.480s	25.874ms	1	1	100.00
V2	rx_timeout	uart_intr	15.480s	25.874ms	1	1	100.00
V2	perf	uart_perf	8.135m	14.995ms	1	1	100.00
V2	sys_loopback	uart_loopback	1.490s	85.040us	1	1	100.00
V2	line_loopback	uart_loopback	1.490s	85.040us	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	21.360s	20.494ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	6.870s	4.998ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.920s	1.784ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	39.500s	5.861ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	1.685m	46.359ms	1	1	100.00
V2	stress_all	uart_stress_all	9.796m	353.798ms	1	1	100.00
V2	alert_test	uart_alert_test	1.380s	23.255us	1	1	100.00
V2	intr_test	uart_intr_test	1.490s	69.989us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.770s	154.319us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.770s	154.319us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.730s	22.108us	1	1	100.00
		uart_csr_rw	1.750s	34.536us	1	1	100.00
		uart_csr_aliasing	1.570s	28.108us	1	1	100.00
		uart_same_csr_outstanding	1.760s	31.132us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.730s	22.108us	1	1	100.00
		uart_csr_rw	1.750s	34.536us	1	1	100.00
		uart_csr_aliasing	1.570s	28.108us	1	1	100.00
		uart_same_csr_outstanding	1.760s	31.132us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.710s	64.817us	1	1	100.00
		uart_tl_intg_err	1.890s	275.212us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.890s	275.212us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	15.180s	8.562ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.28967510304470392954388644124083281230191424609635506042430870111060272998602
      Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @  10504673 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 126363347 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 126363347 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_INFO @ 9976173389 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 1/13
        UVM_INFO @ 12674934937 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 2/13