CHIP Simulation Results

Tuesday June 17 2025 17:02:32 UTC

GitHub Revision: `b69339b`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	6.031m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	6.031m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	6.307m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	5.021m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	4.583m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.648m	4.854ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.648m	4.854ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.648m	4.854ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	26.450s	10.120us	0	1	0.00
		chip_sw_example_manufacturer	6.386m		0	1	0.00
		chip_sw_example_concurrency	4.306m	4.042ms	1	1	100.00
		chip_sw_uart_smoketest_signed	12.326s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	8.420s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	7.760s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	7.760s		0	1	0.00
V1	xbar_smoke	xbar_smoke	8.720s	12.566us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	5.658m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	9.535m	8.157ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.243m	4.074ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.597m		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	3.496m		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	4.399m		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	3.568m		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.420s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.420s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	5.958m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	6.040m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.206m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.206m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.384m	4.321ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.055m	4.530ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.450m	14.383ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.640s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	11.279s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	8.340m	15.868ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	4.724m	5.152ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	21.461m	18.016ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	21.461m	18.016ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	13.436s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.721m	5.299ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.721m	5.299ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	6.966m	18.017ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.194m	5.331ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	5.365m	5.923ms	1	1	100.00
		chip_sw_aes_idle	4.467m	5.393ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.173m	3.749ms	1	1	100.00
		chip_sw_kmac_idle	3.897m	4.133ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	11.754m	12.022ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	12.985m	11.828ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	10.502m	12.026ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	11.202m	12.020ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	16.664s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.695s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	13.386s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.922s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.926s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	14.833s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	15.531s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	16.664s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.695s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	13.386s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.922s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.926s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	14.833s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	15.531s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	15.112s		0	1	0.00
		chip_sw_aes_enc_jitter_en	36.530s	10.300us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	35.420s	10.380us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	36.560s	10.120us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	36.000s	10.180us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.424s		0	1	0.00
		chip_sw_clkmgr_jitter	3.318m	4.029ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.453m	5.297ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	12.759s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	50.410s	10.200us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	37.950s	10.140us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	33.500s	10.320us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	35.340s	10.220us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	33.780s	10.180us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	11.910s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.501s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.256s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	12.705s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	17.765m	16.907ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	9.717m	14.372ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	5.721m	5.299ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	21.070s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	9.717m	14.372ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	38.776s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	22.408s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	1.089m		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	55.653s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	32.365s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	17.765m	16.907ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.450m	14.383ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	20.737m	20.016ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	6.228m	5.684ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	7.478m	6.638ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.176m	5.122ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	17.765m	16.907ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	11.186s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	11.850s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	17.765m	16.907ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	14.532s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	7.478m	6.638ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	16.737s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	14.599s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	13.221s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	14.222s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	11.529s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	11.657s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	11.850s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	1.367m		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	2.418m		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	1.367m		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	1.367m		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	1.367m		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	6.587m	5.925ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.329m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	1.184m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	40.365s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	1.434m		0	1	0.00
		chip_sw_lc_ctrl_transition	1.367m		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	6.486m	6.258ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	9.572m	14.581ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	13.122s		0	1	0.00
		chip_prim_tl_access	14.895m	26.802ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	16.664s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.695s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	13.386s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.922s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.926s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	14.833s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	15.531s		0	1	0.00
		chip_rv_dm_lc_disabled	8.340m	15.868ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.296m	5.947ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	36.530s	10.300us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.786m	3.779ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.467m	5.393ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.233m	3.993ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	35.420s	10.380us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.173m	3.749ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.485m	5.987ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.265m	4.910ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	36.000s	10.180us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	6.486m	6.258ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	1.367m		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	27.930s	10.200us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.343m	4.508ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.897m	4.133ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.673s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.673s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	13.560s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.776m	3.896ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	16.322s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	6.486m	6.258ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	36.560s	10.120us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	17.257s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	15.112s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	5.365m	5.923ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	5.365m	5.923ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	5.365m	5.923ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	9.214m	6.170ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.572m	14.581ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.572m	14.581ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	8.422m	8.331ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.424s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	13.122s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	17.765m	16.907ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.206m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	1.367m		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	9.214m	6.170ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.486m	6.258ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.422m	8.331ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.999m	3.953ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	9.214m	6.170ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.486m	6.258ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.422m	8.331ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.999m	3.953ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	1.367m		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	11.248s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	2.418m		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.329m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	1.184m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	40.365s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	1.434m		0	1	0.00
		chip_sw_lc_ctrl_transition	1.367m		0	1	0.00
		chip_prim_tl_access	14.895m	26.802ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	14.895m	26.802ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	27.737s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	11.350s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.501s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	15.112s		0	1	0.00
		chip_sw_aes_enc_jitter_en	36.530s	10.300us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	35.420s	10.380us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	36.560s	10.120us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	36.000s	10.180us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.424s		0	1	0.00
		chip_sw_clkmgr_jitter	3.318m	4.029ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	7.685m	8.556ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	7.685m	8.556ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	4.049m	5.479ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	3.957m	3.782ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.089m	3.705ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.444m	4.432ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.955m	4.827ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.929m	6.079ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.999m	3.953ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	20.737m	20.016ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	20.737m	20.016ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.943m	5.226ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.428m	5.206ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.882m	4.419ms	1	1	100.00
		chip_sw_csrng_smoketest	2.660m	3.812ms	1	1	100.00
		chip_sw_gpio_smoketest	3.767m	5.684ms	1	1	100.00
		chip_sw_hmac_smoketest	4.005m	5.755ms	1	1	100.00
		chip_sw_kmac_smoketest	3.934m	5.170ms	1	1	100.00
		chip_sw_otbn_smoketest	4.658m	4.772ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.115m	3.418ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.667m	5.118ms	1	1	100.00
		chip_sw_rv_timer_smoketest	3.981m	5.350ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.562m	5.470ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.002m	3.694ms	1	1	100.00
		chip_sw_uart_smoketest	3.030m	3.273ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	14.590s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	12.326s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	5.658m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	15.742s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.435m	5.804ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.896m	5.657ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.521m	4.536ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.577m	4.623ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	13.627s		0	1	0.00
		chip_rv_dm_lc_disabled	8.340m	15.868ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	12.341s		0	1	0.00
		chip_sw_lc_walkthrough_prod	25.735s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	13.326s		0	1	0.00
		chip_sw_lc_walkthrough_rma	15.452s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	13.627s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	22.906s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	17.187s		0	1	0.00
		rom_volatile_raw_unlock	11.039s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	15.125s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	5.225m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	5.077m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.580m	4.320ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.580m	4.320ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	7.760s		0	1	0.00
		chip_same_csr_outstanding	9.710s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	7.760s		0	1	0.00
		chip_same_csr_outstanding	9.710s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	2.475m	422.400us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	12.210s	11.827us	1	1	100.00
		xbar_smoke_large_delays	4.146m	2.302ms	1	1	100.00
		xbar_smoke_slow_rsp	5.494m	2.109ms	1	1	100.00
		xbar_random_zero_delays	29.580s	27.838us	1	1	100.00
		xbar_random_large_delays	4.373m	2.492ms	1	1	100.00
		xbar_random_slow_rsp	26.344m	10.155ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.405m	176.792us	1	1	100.00
		xbar_error_and_unmapped_addr	56.360s	125.891us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	1.112m	193.991us	1	1	100.00
		xbar_error_and_unmapped_addr	56.360s	125.891us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	4.152m	784.276us	1	1	100.00
		xbar_access_same_device_slow_rsp	26.680m	10.298ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	2.348m	454.688us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	14.547m	2.397ms	1	1	100.00
		xbar_stress_all_with_error	12.340s	11.954us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	4.965m	228.308us	1	1	100.00
		xbar_stress_all_with_reset_error	6.076m	677.539us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	12.592s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	13.922s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	12.648s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	13.990s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	11.706s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	11.883s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.929s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	11.418s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.966s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	11.610s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	10.922s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	11.102s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	11.774s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	11.853s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	12.976s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	11.964s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	13.065s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	12.225s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	13.142s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	13.118s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	14.339s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.066s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	12.040s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	12.314s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	12.908s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	13.832s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.441s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.510s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.981s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	13.311s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	13.589s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	14.052s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.348s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	12.407s		0	1	0.00
		rom_e2e_asm_init_dev	12.819s		0	1	0.00
		rom_e2e_asm_init_prod	11.989s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.487s		0	1	0.00
		rom_e2e_asm_init_rma	11.467s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.642s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.566s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	12.821s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	12.279s		0	1	0.00
V2		TOTAL			66	205	32.20
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.732m	4.602ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.393m	4.754ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	12.100s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.145s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.454s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.774s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	17.765m	16.907ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	16.183s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	17.442m	12.481ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	13.067s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	17.392s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	12.100s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.145s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.454s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.484s		0	1	0.00
		rom_e2e_jtag_inject_dev	12.015s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.483s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.437m		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	19.666m	15.672ms	1	1	100.00
		chip_plic_all_irqs_0	9.093m	6.965ms	1	1	100.00
		chip_plic_all_irqs_10	8.976m	7.569ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.115m	6.100ms	1	1	100.00
		chip_sw_dma_abort	3.406m	5.543ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	11.915s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.607s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	12.278s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	10.762s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.826s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.694s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.829s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	12.360s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	10.995s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	10.699s		0	1	0.00
		chip_sw_mbx_smoketest	4.331m	3.440ms	1	1	100.00
		TOTAL			77	247	31.17

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.11065665953085084944742142555734188041657246966022404476209031504050283124610
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (fac7d3)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 367.866s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.78456279796216370612352966415866473955250503383347126130102228035648809138261
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (f4930d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 362.334s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.53159937186974066637559859580458467912303158809246824092763923564295557997103
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Target //sw/device/tests:sleep_pin_wake_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (2c722f)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 346.796s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.81652782311852929447332564767894059833178618132033637119725393602540570811180
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (eeaf24)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 352.328s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.15696648410084027253361808520070784518385404483573734756717385845818700496249
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (b18286)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 351.824s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.102638362949240980188596106705810895315049352338519375686630552798138653666144
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.111213740441563404922639624364100451464560813498913596185328212813964395787253
    Line 431, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.98812783557586216541154801644501214402500347629652272058392799377787948365615
    Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.57281424240057394026105695609847456055054113416431043946361442539065444965562
    Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.52880490221179580145666737642265043775419327577832294202936847889270532322103
    Line 414, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.20075237896246948531553964794557822810061095880442699838079611969602687602751
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.15293086040509076262210069905157812387456255946597222858373067511387845271130
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.84187763216288407713859195285837578976363171653066977213894958951776055032066
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.53727809318046409305021127940215903372797659847166324437356165603041172364621
Line 520, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20016.241465 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20016.241465 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.9456759108444728326843892416247210560475290156268897124474084513476981532735
Line 478, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18016.383340 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18016.383340 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.42884958635410745896865961060411552007120447672220954390683172154820540975910
Line 432, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18016.945966 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18016.945966 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.84740321866743482537571190349050851058059016059057988971237266387109107044917
Line 443, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12021.576031 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12021.576031 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.97335294784244625441035774278788488164202838608890161722907709754226564677815
Line 447, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12025.566537 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12025.566537 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.70896103520347475617144382459608028776093504768337035241037493882177103672408
Line 442, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12019.623115 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12019.623115 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.58487708761863672564803897424529188706757068303351654662821425178013047562800
Line 484, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 6258.300246 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (12718010980147209192744557971273360854477607511656248515820917045755392206679 [0x1c1e239d854e079ec74bc00c94141dc7de0848dedc320bd16b56e226bd1ea757] vs 111041901911258172788841811513852915219222759829705786144872150847228830669166 [0xf57f7d3f885dd00da17baa19a265e5c02adc8355c9e9fe1da2ca0ceb426dd96e])
  UVM_INFO @ 6258.300246 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.21534152248851778689746878548697674834917290771628134125090778311594916622582
Line 485, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 5924.694278 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (105321123060385329590026999078796145880565517282500177799059007417839930385316 [0xe8d9a4a68764bb20271d601b586159007ff4820305fe4de874d3f343cc7923a4] vs 28823139043837008337224663214468083053837887423940673876641832382650175307674 [0x3fb9518e3c35684631e1189df7a5f20165d2751bc80f2774c615de6602c9bf9a])
  UVM_INFO @ 5924.694278 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.88200098300045509171011970566936395428871253151532256284701416316736706990389
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4320.682845 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: 'h30480000  a_data: 'h5d5f9fbc  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h10  a_opcode: 'h0  a_user: 'h26940  d_param: 'h0  d_source: 'h10  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4320.682845 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.83870041558787693893405130830178194369040016210637612403120397503193273880799
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4530.302555 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: 'h30480000  a_data: 'h824cfc52  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2f  a_opcode: 'h1  a_user: 'h248b7  d_param: 'h0  d_source: 'h2f  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4530.302555 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.37747456365010411151595800685182220327487282482512266252640902562336687297008
    Line 1034, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.40336105158310294928186798847614761906068067357834808279425356030656181229390
    Line 468, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4074.091968 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4074.091968 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.33782039074817116321661365160137617750365762159291604703356471646649414142309
    Line 770, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 6637.950328 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 6637.950328 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.21371929529460101666776884539061093616015700718328308784429495264947628994978
    Line 477, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 5478.586454 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5478.586454 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.61658386181412471261803042779874854143232147056119529635744107023585920582253
    Line 481, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 3782.484842 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 3782.484842 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.95093117144832798806656095697145122865834585863218826818441326623577227710500
    Line 466, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 5298.625000 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 5298.625000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.114705001209951521209454341486492043347253153826410458038433054006914231971535
    Line 436, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 4431.832800 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 4431.832800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.110211644795755607369319297921842328136833287909646670051506504681324896224146
    Line 429, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@35948) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.141872862714892009641740569449144291291175298940791478616493434853787817327
Line 263, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 4320.270646 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@35948) { a_addr: 'h2213  a_data: 'h6da04243  a_mask: 'h8  a_size: 'h0  a_param: 'h0  a_source: 'hc1  a_opcode: 'h4  a_user: 'h242f3  d_param: 'h0  d_source: 'hc1  d_data: 'h0  d_size: 'h0  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'h4aa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4320.270646 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.84625650636272129073321144415799265842624215475749581662719325075875360890907
    Line 402, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14383.363972 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14383.363972 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.80305893316986180430411967766324848159675215666108624285092994477350357284885
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 96
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.37075998770270823588472028577888965614237460225711520383235664209553944635982
    Line 428, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 5542.831370 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 5542.831370 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```