CSRNG Simulation Results

Wednesday June 18 2025 17:01:10 UTC

GitHub Revision: 952e1dd

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	75.922us	1	1	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	5.000s	13.666us	1	1	100.00
V1	csr_rw	csrng_csr_rw	6.000s	152.611us	1	1	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	24.000s	937.357us	1	1	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	97.091us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	148.230us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	6.000s	152.611us	1	1	100.00
		csrng_csr_aliasing	6.000s	97.091us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	interrupts	csrng_intr	6.000s	56.075us	1	1	100.00
V2	alerts	csrng_alert	6.000s	118.746us	1	1	100.00
V2	err	csrng_err	4.000s	7.634us	0	1	0.00
V2	cmds	csrng_cmds	1.017m	4.128ms	1	1	100.00
V2	life cycle	csrng_cmds	1.017m	4.128ms	1	1	100.00
V2	stress_all	csrng_stress_all	24.000s	532.075us	1	1	100.00
V2	intr_test	csrng_intr_test	5.000s	70.878us	1	1	100.00
V2	alert_test	csrng_alert_test	5.000s	23.681us	1	1	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	7.000s	145.369us	1	1	100.00
V2	tl_d_illegal_access	csrng_tl_errors	7.000s	145.369us	1	1	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	5.000s	13.666us	1	1	100.00
		csrng_csr_rw	6.000s	152.611us	1	1	100.00
		csrng_csr_aliasing	6.000s	97.091us	1	1	100.00
		csrng_same_csr_outstanding	5.000s	43.541us	1	1	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	5.000s	13.666us	1	1	100.00
		csrng_csr_rw	6.000s	152.611us	1	1	100.00
		csrng_csr_aliasing	6.000s	97.091us	1	1	100.00
		csrng_same_csr_outstanding	5.000s	43.541us	1	1	100.00
V2		TOTAL			8	9	88.89
V2S	tl_intg_err	csrng_sec_cm	5.000s	51.742us	1	1	100.00
		csrng_tl_intg_err	5.000s	44.779us	1	1	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	32.946us	1	1	100.00
		csrng_csr_rw	6.000s	152.611us	1	1	100.00
V2S	sec_cm_config_mubi	csrng_alert	6.000s	118.746us	1	1	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	24.000s	532.075us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	6.000s	56.075us	1	1	100.00
		csrng_err	4.000s	7.634us	0	1	0.00
		csrng_sec_cm	5.000s	51.742us	1	1	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	6.000s	56.075us	1	1	100.00
		csrng_err	4.000s	7.634us	0	1	0.00
		csrng_sec_cm	5.000s	51.742us	1	1	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	6.000s	56.075us	1	1	100.00
		csrng_err	4.000s	7.634us	0	1	0.00
		csrng_sec_cm	5.000s	51.742us	1	1	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	6.000s	56.075us	1	1	100.00
		csrng_err	4.000s	7.634us	0	1	0.00
		csrng_sec_cm	5.000s	51.742us	1	1	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	6.000s	56.075us	1	1	100.00
		csrng_err	4.000s	7.634us	0	1	0.00
		csrng_sec_cm	5.000s	51.742us	1	1	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	6.000s	56.075us	1	1	100.00
		csrng_err	4.000s	7.634us	0	1	0.00
		csrng_sec_cm	5.000s	51.742us	1	1	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	6.000s	56.075us	1	1	100.00
		csrng_err	4.000s	7.634us	0	1	0.00
		csrng_sec_cm	5.000s	51.742us	1	1	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	6.000s	118.746us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	6.000s	56.075us	1	1	100.00
		csrng_err	4.000s	7.634us	0	1	0.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	24.000s	532.075us	1	1	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	6.000s	118.746us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	5.000s	44.779us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	6.000s	56.075us	1	1	100.00
		csrng_err	4.000s	7.634us	0	1	0.00
		csrng_sec_cm	5.000s	51.742us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	6.000s	56.075us	1	1	100.00
		csrng_err	4.000s	7.634us	0	1	0.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	6.000s	56.075us	1	1	100.00
		csrng_err	4.000s	7.634us	0	1	0.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	6.000s	56.075us	1	1	100.00
		csrng_err	4.000s	7.634us	0	1	0.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	6.000s	56.075us	1	1	100.00
		csrng_err	4.000s	7.634us	0	1	0.00
		csrng_sec_cm	5.000s	51.742us	1	1	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	6.000s	56.075us	1	1	100.00
		csrng_err	4.000s	7.634us	0	1	0.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	50.000s	1.934ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			17	19	89.47

Failure Buckets

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_cipher_control_fsm.sv,452): Assertion u_state_regs_A has failed has 1 failures:

  • Test csrng_err has 1 failures.

    • 0.csrng_err.49159932467700041486670866598129610172134946699703393680052560064854333818509
      Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_control_fsm.sv,452): (time 7634287 PS) Assertion tb.dut.u_csrng_core.u_csrng_block_encrypt.u_aes_cipher_core.u_aes_cipher_control.gen_fsm[0].gen_fsm_p.u_aes_cipher_control_fsm_i.u_aes_cipher_control_fsm.u_state_regs_A has failed
        UVM_ERROR @   7634287 ps: (aes_cipher_control_fsm.sv:452) [ASSERT FAILED] u_state_regs_A
        UVM_INFO @   7634287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:929) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test csrng_stress_all_with_rand_reset has 1 failures.

    • 0.csrng_stress_all_with_rand_reset.58429097342558424553861097203482271297097919569089487671055571504205886285104
      Line 111, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1934259117 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1934259117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---