DMA Simulation Results

Wednesday June 18 2025 17:01:10 UTC

GitHub Revision: 952e1dd

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	8.000s	287.636us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	9.000s	844.135us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	7.000s	1.091ms	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	28.491us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	20.126us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	12.000s	3.604ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	8.000s	604.567us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	103.011us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	20.126us	1	1	100.00
		dma_csr_aliasing	8.000s	604.567us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.283m	4.065ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	36.883m	242.937ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	40.617m	300.057ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	37.700m	245.594ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	36.883m	242.937ms	1	1	100.00
V2	dma_abort	dma_abort	7.000s	484.228us	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.633m	15.069ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	42.572us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	5.000s	29.081us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	5.000s	29.081us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	28.491us	1	1	100.00
		dma_csr_rw	4.000s	20.126us	1	1	100.00
		dma_csr_aliasing	8.000s	604.567us	1	1	100.00
		dma_same_csr_outstanding	4.000s	113.934us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	28.491us	1	1	100.00
		dma_csr_rw	4.000s	20.126us	1	1	100.00
		dma_csr_aliasing	8.000s	604.567us	1	1	100.00
		dma_same_csr_outstanding	4.000s	113.934us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	23.000s	976.206us	1	1	100.00
		dma_generic_stress	37.700m	245.594ms	1	1	100.00
		dma_handshake_stress	36.883m	242.937ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	5.000s	96.017us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	1.050m	26.608ms	1	1	100.00
		dma_longer_transfer	6.000s	413.923us	1	1	100.00
		TOTAL			21	21	100.00