EDN Simulation Results

Wednesday June 18 2025 17:01:10 UTC

GitHub Revision: 952e1dd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.820s	26.125us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.740s	17.193us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.840s	50.127us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.220s	114.108us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.740s	113.107us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.930s	84.218us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.840s	50.127us	1	1	100.00
		edn_csr_aliasing	1.740s	113.107us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.210s	42.230us	1	1	100.00
V2	csrng_commands	edn_genbits	2.210s	42.230us	1	1	100.00
V2	genbits	edn_genbits	2.210s	42.230us	1	1	100.00
V2	interrupts	edn_intr	1.920s	25.604us	1	1	100.00
V2	alerts	edn_alert	1.860s	232.648us	1	1	100.00
V2	errs	edn_err	1.890s	30.379us	1	1	100.00
V2	disable	edn_disable	1.680s	11.650us	1	1	100.00
		edn_disable_auto_req_mode	1.840s	86.836us	1	1	100.00
V2	stress_all	edn_stress_all	4.590s	674.208us	1	1	100.00
V2	intr_test	edn_intr_test	2.120s	30.375us	1	1	100.00
V2	alert_test	edn_alert_test	1.710s	60.794us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.580s	224.413us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.580s	224.413us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.740s	17.193us	1	1	100.00
		edn_csr_rw	1.840s	50.127us	1	1	100.00
		edn_csr_aliasing	1.740s	113.107us	1	1	100.00
		edn_same_csr_outstanding	1.850s	19.633us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.740s	17.193us	1	1	100.00
		edn_csr_rw	1.840s	50.127us	1	1	100.00
		edn_csr_aliasing	1.740s	113.107us	1	1	100.00
		edn_same_csr_outstanding	1.850s	19.633us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	4.790s	502.296us	1	1	100.00
		edn_tl_intg_err	2.860s	924.171us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.810s	25.682us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.860s	232.648us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	4.790s	502.296us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	4.790s	502.296us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	4.790s	502.296us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	4.790s	502.296us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.860s	232.648us	1	1	100.00
		edn_sec_cm	4.790s	502.296us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.860s	232.648us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.860s	924.171us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.803m	24.483ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00