HMAC Simulation Results

Wednesday June 18 2025 17:01:10 UTC

GitHub Revision: 952e1dd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 7.170s 10.102ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.600s 78.401us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.630s 36.008us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 13.090s 1.654ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.220s 162.683us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.670s 458.222us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.630s 36.008us 1 1 100.00
hmac_csr_aliasing 3.220s 162.683us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 7.930s 441.148us 1 1 100.00
V2 back_pressure hmac_back_pressure 42.010s 872.763us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 9.050s 164.027us 1 1 100.00
hmac_test_sha384_vectors 5.833m 11.447ms 1 1 100.00
hmac_test_sha512_vectors 5.260m 21.655ms 1 1 100.00
hmac_test_hmac256_vectors 10.750s 595.846us 1 1 100.00
hmac_test_hmac384_vectors 9.590s 300.603us 1 1 100.00
hmac_test_hmac512_vectors 7.230s 1.801ms 1 1 100.00
V2 burst_wr hmac_burst_wr 7.030s 129.873us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 6.141m 10.833ms 1 1 100.00
V2 error hmac_error 1.209m 16.829ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 50.370s 5.108ms 1 1 100.00
V2 save_and_restore hmac_smoke 7.170s 10.102ms 1 1 100.00
hmac_long_msg 7.930s 441.148us 1 1 100.00
hmac_back_pressure 42.010s 872.763us 1 1 100.00
hmac_datapath_stress 6.141m 10.833ms 1 1 100.00
hmac_burst_wr 7.030s 129.873us 1 1 100.00
hmac_stress_all 3.087m 13.235ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 7.170s 10.102ms 1 1 100.00
hmac_long_msg 7.930s 441.148us 1 1 100.00
hmac_back_pressure 42.010s 872.763us 1 1 100.00
hmac_datapath_stress 6.141m 10.833ms 1 1 100.00
hmac_wipe_secret 50.370s 5.108ms 1 1 100.00
hmac_test_sha256_vectors 9.050s 164.027us 1 1 100.00
hmac_test_sha384_vectors 5.833m 11.447ms 1 1 100.00
hmac_test_sha512_vectors 5.260m 21.655ms 1 1 100.00
hmac_test_hmac256_vectors 10.750s 595.846us 1 1 100.00
hmac_test_hmac384_vectors 9.590s 300.603us 1 1 100.00
hmac_test_hmac512_vectors 7.230s 1.801ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 7.170s 10.102ms 1 1 100.00
hmac_long_msg 7.930s 441.148us 1 1 100.00
hmac_back_pressure 42.010s 872.763us 1 1 100.00
hmac_datapath_stress 6.141m 10.833ms 1 1 100.00
hmac_burst_wr 7.030s 129.873us 1 1 100.00
hmac_error 1.209m 16.829ms 1 1 100.00
hmac_wipe_secret 50.370s 5.108ms 1 1 100.00
hmac_test_sha256_vectors 9.050s 164.027us 1 1 100.00
hmac_test_sha384_vectors 5.833m 11.447ms 1 1 100.00
hmac_test_sha512_vectors 5.260m 21.655ms 1 1 100.00
hmac_test_hmac256_vectors 10.750s 595.846us 1 1 100.00
hmac_test_hmac384_vectors 9.590s 300.603us 1 1 100.00
hmac_test_hmac512_vectors 7.230s 1.801ms 1 1 100.00
hmac_stress_all 3.087m 13.235ms 1 1 100.00
V2 stress_all hmac_stress_all 3.087m 13.235ms 1 1 100.00
V2 alert_test hmac_alert_test 1.590s 53.015us 1 1 100.00
V2 intr_test hmac_intr_test 1.570s 13.729us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.270s 43.895us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.270s 43.895us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.600s 78.401us 1 1 100.00
hmac_csr_rw 1.630s 36.008us 1 1 100.00
hmac_csr_aliasing 3.220s 162.683us 1 1 100.00
hmac_same_csr_outstanding 2.140s 77.912us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.600s 78.401us 1 1 100.00
hmac_csr_rw 1.630s 36.008us 1 1 100.00
hmac_csr_aliasing 3.220s 162.683us 1 1 100.00
hmac_same_csr_outstanding 2.140s 77.912us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.940s 93.827us 1 1 100.00
hmac_tl_intg_err 2.420s 713.081us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.420s 713.081us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 7.170s 10.102ms 1 1 100.00
V3 stress_reset hmac_stress_reset 1.690s 71.259us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 10.280s 3.206ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 3.000s 379.327us 1 1 100.00
TOTAL 28 28 100.00