I2C Simulation Results

Wednesday June 18 2025 17:01:10 UTC

GitHub Revision: `952e1dd`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	21.860s	2.924ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	15.320s	19.067ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.610s	37.767us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.720s	88.033us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.980s	463.941us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.320s	39.627us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.720s	32.709us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.720s	88.033us	1	1	100.00
		i2c_csr_aliasing	2.320s	39.627us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.390s	84.780us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	6.980m	11.128ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	20.520s	2.618ms	1	1	100.00
V2	host_override	i2c_host_override	1.480s	98.116us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.316m	21.195ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	42.430s	18.516ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.840s	345.204us	1	1	100.00
		i2c_host_fifo_fmt_empty	4.390s	874.963us	1	1	100.00
		i2c_host_fifo_reset_rx	7.620s	318.875us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	36.300s	16.882ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	7.340s	590.995us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.450s	91.466us	0	1	0.00
V2	target_glitch	i2c_target_glitch	7.020s	1.866ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	52.890s	52.982ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.190s	449.293us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	25.560s	3.291ms	1	1	100.00
		i2c_target_intr_smoke	5.530s	672.667us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.620s	268.707us	1	1	100.00
		i2c_target_fifo_reset_tx	1.960s	380.954us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	3.998m	54.508ms	1	1	100.00
		i2c_target_stress_rd	25.560s	3.291ms	1	1	100.00
		i2c_target_intr_stress_wr	5.490s	8.382ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.530s	1.125ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	29.750s	4.512ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.520s	4.138ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	19.160s	10.080ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.330s	556.016us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.290s	259.242us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	20.520s	2.618ms	1	1	100.00
		i2c_host_perf_precise	4.510s	1.232ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	7.340s	590.995us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.530s	99.007us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.330s	435.436us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.920s	2.268ms	1	1	100.00
		i2c_target_nack_txstretch	2.700s	1.009ms	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	13.380s	2.911ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	3.570s	1.004ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.620s	15.572us	1	1	100.00
V2	intr_test	i2c_intr_test	1.620s	115.323us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.060s	48.675us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.060s	48.675us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.610s	37.767us	1	1	100.00
		i2c_csr_rw	1.720s	88.033us	1	1	100.00
		i2c_csr_aliasing	2.320s	39.627us	1	1	100.00
		i2c_same_csr_outstanding	1.770s	20.767us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.610s	37.767us	1	1	100.00
		i2c_csr_rw	1.720s	88.033us	1	1	100.00
		i2c_csr_aliasing	2.320s	39.627us	1	1	100.00
		i2c_same_csr_outstanding	1.770s	20.767us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	2.200s	96.737us	1	1	100.00
		i2c_sec_cm	1.870s	106.029us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.200s	96.737us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	15.280s	1.081ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.840s	88.644us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	8.450s	689.260us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.44585173717878047769192276794707263662167972725103481338092856503147485019020
    Line 87, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1080759330 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1080759330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.6312881029354908497631281592044691464967908057923897258581879070901338965187
    Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 689259911 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 689259911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.60145817693976151971041668989410540878173876736021036148008481136493833118082
Line 115, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 11127965745 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @4129786

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.73549993740393831329768316324705144569403980305942107481330232461520477162414
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  88643717 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 17 [0x11])
  UVM_INFO @  88643717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 0.i2c_target_hrst.4508194721479175901853503548553931429654019331140154060665826840203267554655
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10080445244 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10080445244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 0.i2c_host_mode_toggle.77726208711218911005717841558485491131072015714954023603530608079800092766431
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  91465911 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0x3cffe114, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  91465911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```