KEYMGR Simulation Results

Wednesday June 18 2025 17:01:10 UTC

GitHub Revision: 952e1dd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.380s	37.704us	1	1	100.00
V1	random	keymgr_random	4.290s	240.541us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.830s	71.672us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.980s	35.324us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	4.150s	147.708us	0	1	0.00
V1	csr_aliasing	keymgr_csr_aliasing	3.920s	264.869us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.380s	84.210us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.980s	35.324us	1	1	100.00
		keymgr_csr_aliasing	3.920s	264.869us	1	1	100.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	10.990s	276.492us	1	1	100.00
V2	sideload	keymgr_sideload	4.990s	141.392us	1	1	100.00
		keymgr_sideload_kmac	2.590s	40.168us	1	1	100.00
		keymgr_sideload_aes	4.100s	255.095us	1	1	100.00
		keymgr_sideload_otbn	2.350s	72.904us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	3.050s	104.717us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.160s	95.197us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	7.170s	396.977us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	15.380s	3.248ms	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	3.930s	883.861us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.980s	155.428us	1	1	100.00
V2	stress_all	keymgr_stress_all	5.020m	39.148ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.700s	14.910us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.740s	222.306us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.440s	93.066us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.440s	93.066us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.830s	71.672us	1	1	100.00
		keymgr_csr_rw	1.980s	35.324us	1	1	100.00
		keymgr_csr_aliasing	3.920s	264.869us	1	1	100.00
		keymgr_same_csr_outstanding	2.210s	41.472us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.830s	71.672us	1	1	100.00
		keymgr_csr_rw	1.980s	35.324us	1	1	100.00
		keymgr_csr_aliasing	3.920s	264.869us	1	1	100.00
		keymgr_same_csr_outstanding	2.210s	41.472us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	14.820s	852.956us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	14.820s	852.956us	1	1	100.00
		keymgr_tl_intg_err	2.530s	70.821us	0	1	0.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.730s	107.788us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.730s	107.788us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.730s	107.788us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.730s	107.788us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	1.930s	66.342us	0	1	0.00
V2S	prim_count_check	keymgr_sec_cm	14.820s	852.956us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	14.820s	852.956us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	2.530s	70.821us	0	1	0.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.730s	107.788us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	10.990s	276.492us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	4.290s	240.541us	1	1	100.00
		keymgr_csr_rw	1.980s	35.324us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	4.290s	240.541us	1	1	100.00
		keymgr_csr_rw	1.980s	35.324us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	4.290s	240.541us	1	1	100.00
		keymgr_csr_rw	1.980s	35.324us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.160s	95.197us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	3.930s	883.861us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	3.930s	883.861us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	4.290s	240.541us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.750s	204.621us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	14.820s	852.956us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	14.820s	852.956us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	14.820s	852.956us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.840s	58.184us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.160s	95.197us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	14.820s	852.956us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	14.820s	852.956us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	14.820s	852.956us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.840s	58.184us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.840s	58.184us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	14.820s	852.956us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.840s	58.184us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	14.820s	852.956us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.840s	58.184us	1	1	100.00
V2S		TOTAL			4	6	66.67
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	12.460s	398.352us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			26	30	86.67

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 3 failures:

  • Test keymgr_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.keymgr_shadow_reg_errors_with_csr_rw.26985808582352811206475881160640375396189150203823214442923375499094245281370
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[12] & 'hffffffff)))'
        UVM_ERROR @  66342422 ps: (keymgr_csr_assert_fpv.sv:442) [ASSERT FAILED] sealing_sw_binding_7_rd_A
        UVM_INFO @  66342422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_tl_intg_err has 1 failures.

    • 0.keymgr_tl_intg_err.38651432586511536070980758403583368966983527731378450442322002502206068096785
      Line 103, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
        UVM_ERROR @  70821188 ps: (keymgr_csr_assert_fpv.sv:478) [ASSERT FAILED] attest_sw_binding_5_rd_A
        UVM_INFO @  70821188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_bit_bash has 1 failures.

    • 0.keymgr_csr_bit_bash.10889452464010685385803656574482444078843886160076146197500785145299809446207
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[9] & 'hffffffff)))'
        UVM_ERROR @ 147708121 ps: (keymgr_csr_assert_fpv.sv:424) [ASSERT FAILED] sealing_sw_binding_4_rd_A
        UVM_INFO @ 147708121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.145977047774883719768981908681574282522344516035299093379340439339633869361
      Line 1127, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 398351613 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
        UVM_INFO @ 398351613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---