KMAC/MASKED Simulation Results

Wednesday June 18 2025 17:01:10 UTC

GitHub Revision: 952e1dd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	26.270s	1.593ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.840s	45.307us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.970s	172.794us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	14.390s	4.015ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.520s	785.046us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.360s	155.380us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.970s	172.794us	1	1	100.00
		kmac_csr_aliasing	4.520s	785.046us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.600s	10.478us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.350s	119.696us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	19.216m	140.444ms	1	1	100.00
V2	burst_write	kmac_burst_write	1.746m	5.120ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	37.490s	6.437ms	1	1	100.00
		kmac_test_vectors_sha3_256	42.070s	45.435ms	1	1	100.00
		kmac_test_vectors_sha3_384	22.640s	3.563ms	1	1	100.00
		kmac_test_vectors_sha3_512	17.249m	133.887ms	1	1	100.00
		kmac_test_vectors_shake_128	2.441m	58.456ms	1	1	100.00
		kmac_test_vectors_shake_256	1.499m	7.258ms	1	1	100.00
		kmac_test_vectors_kmac	3.600s	297.832us	1	1	100.00
		kmac_test_vectors_kmac_xof	4.420s	346.447us	1	1	100.00
V2	sideload	kmac_sideload	2.656m	24.365ms	1	1	100.00
V2	app	kmac_app	1.298m	4.598ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.785m	13.861ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.000m	6.768ms	1	1	100.00
V2	error	kmac_error	3.484m	4.940ms	1	1	100.00
V2	key_error	kmac_key_error	3.230s	263.252us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.250s	131.837us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	34.010s	2.345ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	2.050s	36.590us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.079m	15.030ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.630s	149.005us	1	1	100.00
V2	stress_all	kmac_stress_all	12.556m	50.774ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.600s	15.060us	1	1	100.00
V2	alert_test	kmac_alert_test	1.620s	26.084us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.150s	57.843us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.150s	57.843us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.840s	45.307us	1	1	100.00
		kmac_csr_rw	1.970s	172.794us	1	1	100.00
		kmac_csr_aliasing	4.520s	785.046us	1	1	100.00
		kmac_same_csr_outstanding	3.660s	236.349us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.840s	45.307us	1	1	100.00
		kmac_csr_rw	1.970s	172.794us	1	1	100.00
		kmac_csr_aliasing	4.520s	785.046us	1	1	100.00
		kmac_same_csr_outstanding	3.660s	236.349us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.930s	221.195us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.930s	221.195us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.930s	221.195us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.930s	221.195us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.830s	368.572us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	43.500s	9.373ms	1	1	100.00
		kmac_tl_intg_err	1.760s	11.885us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.760s	11.885us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.630s	149.005us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	26.270s	1.593ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.656m	24.365ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.930s	221.195us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	43.500s	9.373ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	43.500s	9.373ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	43.500s	9.373ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	26.270s	1.593ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.630s	149.005us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	43.500s	9.373ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.543m	16.208ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	26.270s	1.593ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.578m	1.303ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.12710077271880817863046153435923796621660425429078875336882233227683215511082
      Line 164, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1303296537 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 1303296537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.49363553842687414363960870313190943534357773709477249815620173287618603289612
      Line 82, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[43] & 'hffffffff)))'
        UVM_ERROR @  11885113 ps: (kmac_csr_assert_fpv.sv:524) [ASSERT FAILED] prefix_4_rd_A
        UVM_INFO @  11885113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---