KMAC/UNMASKED Simulation Results

Wednesday June 18 2025 17:01:10 UTC

GitHub Revision: 952e1dd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	17.800s	5.449ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.700s	25.732us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.790s	13.934us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	10.260s	297.218us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.580s	139.627us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.480s	157.479us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.790s	13.934us	1	1	100.00
		kmac_csr_aliasing	3.580s	139.627us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.520s	62.956us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.850s	55.558us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	20.362m	18.373ms	1	1	100.00
V2	burst_write	kmac_burst_write	5.893m	14.268ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	23.628m	62.493ms	1	1	100.00
		kmac_test_vectors_sha3_256	24.977m	79.825ms	1	1	100.00
		kmac_test_vectors_sha3_384	13.972m	12.941ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.920s	3.739ms	1	1	100.00
		kmac_test_vectors_shake_128	2.576m	14.482ms	1	1	100.00
		kmac_test_vectors_shake_256	1.124m	3.268ms	1	1	100.00
		kmac_test_vectors_kmac	2.360s	61.597us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.380s	179.458us	1	1	100.00
V2	sideload	kmac_sideload	4.302m	17.099ms	1	1	100.00
V2	app	kmac_app	2.152m	8.035ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.419m	19.194ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.435m	5.041ms	1	1	100.00
V2	error	kmac_error	1.585m	5.219ms	1	1	100.00
V2	key_error	kmac_key_error	2.810s	2.775ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.390s	217.433us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	2.460s	152.543us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	20.040s	1.566ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	8.880s	1.386ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.020s	65.067us	1	1	100.00
V2	stress_all	kmac_stress_all	12.573m	15.658ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.470s	11.249us	1	1	100.00
V2	alert_test	kmac_alert_test	1.720s	19.137us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.150s	111.848us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.150s	111.848us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.700s	25.732us	1	1	100.00
		kmac_csr_rw	1.790s	13.934us	1	1	100.00
		kmac_csr_aliasing	3.580s	139.627us	1	1	100.00
		kmac_same_csr_outstanding	2.180s	61.091us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.700s	25.732us	1	1	100.00
		kmac_csr_rw	1.790s	13.934us	1	1	100.00
		kmac_csr_aliasing	3.580s	139.627us	1	1	100.00
		kmac_same_csr_outstanding	2.180s	61.091us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.010s	133.282us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.010s	133.282us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.010s	133.282us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.010s	133.282us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.910s	24.141us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	51.660s	29.240ms	1	1	100.00
		kmac_tl_intg_err	3.680s	390.186us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.680s	390.186us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.020s	65.067us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	17.800s	5.449ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	4.302m	17.099ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.010s	133.282us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	51.660s	29.240ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	51.660s	29.240ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	51.660s	29.240ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	17.800s	5.449ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.020s	65.067us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	51.660s	29.240ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	13.140s	817.141us	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	17.800s	5.449ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.528m	2.450ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.45252460716273590201128787488585850568770146505373542078827978346156400646282
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[46] & 'hffffffff)))'
        UVM_ERROR @  24140721 ps: (kmac_csr_assert_fpv.sv:542) [ASSERT FAILED] prefix_7_rd_A
        UVM_INFO @  24140721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---