OTBN Simulation Results

Wednesday June 18 2025 17:01:10 UTC

GitHub Revision: 952e1dd

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	70.422us	1	1	100.00
V1	single_binary	otbn_single	8.000s	52.051us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	19.128us	1	1	100.00
V1	csr_rw	otbn_csr_rw	7.000s	21.808us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	6.000s	173.335us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	17.935us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	7.000s	30.828us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	21.808us	1	1	100.00
		otbn_csr_aliasing	6.000s	17.935us	1	1	100.00
V1	mem_walk	otbn_mem_walk	13.000s	659.220us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	10.000s	1.260ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	26.000s	240.683us	1	1	100.00
V2	multi_error	otbn_multi_err	40.000s	1.067ms	1	1	100.00
V2	back_to_back	otbn_multi	1.300m	235.667us	1	1	100.00
V2	stress_all	otbn_stress_all	20.000s	167.239us	1	1	100.00
V2	lc_escalation	otbn_escalate	10.000s	68.800us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	28.309us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	8.000s	54.827us	1	1	100.00
V2	alert_test	otbn_alert_test	7.000s	71.150us	1	1	100.00
V2	intr_test	otbn_intr_test	6.000s	12.515us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	9.000s	44.478us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	9.000s	44.478us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	19.128us	1	1	100.00
		otbn_csr_rw	7.000s	21.808us	1	1	100.00
		otbn_csr_aliasing	6.000s	17.935us	1	1	100.00
		otbn_same_csr_outstanding	5.000s	17.319us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	19.128us	1	1	100.00
		otbn_csr_rw	7.000s	21.808us	1	1	100.00
		otbn_csr_aliasing	6.000s	17.935us	1	1	100.00
		otbn_same_csr_outstanding	5.000s	17.319us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	8.000s	26.399us	1	1	100.00
		otbn_dmem_err	9.000s	56.206us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	9.000s	52.098us	1	1	100.00
		otbn_controller_ispr_rdata_err	14.000s	78.054us	1	1	100.00
		otbn_mac_bignum_acc_err	14.000s	62.771us	1	1	100.00
		otbn_urnd_err	8.000s	19.430us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	6.000s	55.009us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	11.000s	23.872us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	9.000s	36.808us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	2.483m	1.416ms	1	1	100.00
		otbn_tl_intg_err	24.000s	339.138us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	15.000s	370.973us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	2.483m	1.416ms	1	1	100.00
V2S	prim_count_check	otbn_sec_cm	2.483m	1.416ms	1	1	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	70.422us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	9.000s	56.206us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	8.000s	26.399us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	24.000s	339.138us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	10.000s	68.800us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	8.000s	26.399us	1	1	100.00
		otbn_dmem_err	9.000s	56.206us	1	1	100.00
		otbn_zero_state_err_urnd	9.000s	28.309us	1	1	100.00
		otbn_illegal_mem_acc	6.000s	55.009us	1	1	100.00
		otbn_sec_cm	2.483m	1.416ms	1	1	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	2.483m	1.416ms	1	1	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	8.000s	52.051us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	8.000s	26.399us	1	1	100.00
		otbn_dmem_err	9.000s	56.206us	1	1	100.00
		otbn_zero_state_err_urnd	9.000s	28.309us	1	1	100.00
		otbn_illegal_mem_acc	6.000s	55.009us	1	1	100.00
		otbn_sec_cm	2.483m	1.416ms	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	2.483m	1.416ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	10.000s	68.800us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	8.000s	26.399us	1	1	100.00
		otbn_dmem_err	9.000s	56.206us	1	1	100.00
		otbn_zero_state_err_urnd	9.000s	28.309us	1	1	100.00
		otbn_illegal_mem_acc	6.000s	55.009us	1	1	100.00
		otbn_sec_cm	2.483m	1.416ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	2.483m	1.416ms	1	1	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	8.000s	52.051us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	7.000s	48.927us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	12.715us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	19.000s	720.884us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	19.000s	720.884us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	9.000s	196.042us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	2.483m	1.416ms	1	1	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	2.483m	1.416ms	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	8.000s	170.425us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	2.483m	1.416ms	1	1	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	2.483m	1.416ms	1	1	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	7.000s	50.883us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	7.000s	50.883us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	6.000s	9.643us	1	1	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	8.000s	52.051us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	8.000s	52.051us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	8.000s	52.051us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.300m	235.667us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	8.000s	52.051us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	8.000s	52.051us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	36.000s	652.440us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	8.000s	52.051us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	2.483m	1.416ms	1	1	100.00
V2S		TOTAL			20	20	100.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	3.000m	1.933ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			40	41	97.56

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.40305048193099026779714474640570232040921288099403254485379199228454294460925
      Line 174, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1933375713 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1933375713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---