ROM_CTRL/64KB Simulation Results

Wednesday June 18 2025 17:01:10 UTC

GitHub Revision: 952e1dd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 12.580s 982.319us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 12.580s 1.609ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.210s 726.460us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.540s 206.883us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.980s 214.463us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 8.290s 1.037ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.210s 726.460us 1 1 100.00
rom_ctrl_csr_aliasing 7.980s 214.463us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 5.380s 650.617us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.600s 1.942ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 6.860s 776.651us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 27.870s 1.063ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 13.000s 6.223ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 5.770s 369.741us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.260s 557.019us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.260s 557.019us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 12.580s 1.609ms 1 1 100.00
rom_ctrl_csr_rw 6.210s 726.460us 1 1 100.00
rom_ctrl_csr_aliasing 7.980s 214.463us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.660s 1.538ms 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 12.580s 1.609ms 1 1 100.00
rom_ctrl_csr_rw 6.210s 726.460us 1 1 100.00
rom_ctrl_csr_aliasing 7.980s 214.463us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.660s 1.538ms 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.387m 1.991ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 20.530s 1.465ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.408m 391.246us 1 1 100.00
rom_ctrl_tl_intg_err 1.170m 1.295ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.408m 391.246us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.408m 391.246us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.387m 1.991ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.387m 1.991ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.387m 1.991ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.387m 1.991ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.387m 1.991ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.408m 391.246us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.408m 391.246us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 12.580s 982.319us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 12.580s 982.319us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 12.580s 982.319us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.170m 1.295ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.387m 1.991ms 1 1 100.00
rom_ctrl_kmac_err_chk 13.000s 6.223ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.387m 1.991ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.387m 1.991ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.387m 1.991ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 20.530s 1.465ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.408m 391.246us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 2.188m 4.718ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00