| V1 |
random |
rv_timer_random |
1.730s |
19.217us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
rv_timer_csr_hw_reset |
1.570s |
16.195us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
rv_timer_csr_rw |
1.620s |
40.379us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
rv_timer_csr_bit_bash |
3.400s |
1.360ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
rv_timer_csr_aliasing |
1.780s |
63.636us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
rv_timer_csr_mem_rw_with_rand_reset |
2.060s |
74.844us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
rv_timer_csr_rw |
1.620s |
40.379us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.780s |
63.636us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
random_reset |
rv_timer_random_reset |
1.870s |
106.700us |
1 |
1 |
100.00 |
| V2 |
disabled |
rv_timer_disabled |
1.790s |
93.232us |
1 |
1 |
100.00 |
| V2 |
cfg_update_on_fly |
rv_timer_cfg_update_on_fly |
4.217m |
252.415ms |
1 |
1 |
100.00 |
| V2 |
no_interrupt_test |
rv_timer_cfg_update_on_fly |
4.217m |
252.415ms |
1 |
1 |
100.00 |
| V2 |
stress |
rv_timer_stress_all |
3.260s |
6.073ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
rv_timer_alert_test |
1.520s |
14.608us |
1 |
1 |
100.00 |
| V2 |
intr_test |
rv_timer_intr_test |
1.750s |
62.931us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
rv_timer_tl_errors |
1.780s |
313.763us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
rv_timer_tl_errors |
1.780s |
313.763us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
rv_timer_csr_hw_reset |
1.570s |
16.195us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
1.620s |
40.379us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.780s |
63.636us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
1.690s |
32.673us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
rv_timer_csr_hw_reset |
1.570s |
16.195us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
1.620s |
40.379us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.780s |
63.636us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
1.690s |
32.673us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2S |
tl_intg_err |
rv_timer_sec_cm |
1.960s |
473.346us |
1 |
1 |
100.00 |
|
|
rv_timer_tl_intg_err |
2.020s |
72.672us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
rv_timer_tl_intg_err |
2.020s |
72.672us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
min_value |
rv_timer_min |
1.530s |
41.545us |
1 |
1 |
100.00 |
| V3 |
max_value |
rv_timer_max |
1.590s |
43.067us |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
rv_timer_stress_all_with_rand_reset |
11.630s |
4.448ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
3 |
3 |
100.00 |
|
|
TOTAL |
|
|
19 |
19 |
100.00 |