SPI_DEVICE/1R1W Simulation Results

Wednesday June 18 2025 17:01:10 UTC

GitHub Revision: 952e1dd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	4.843m	100.258ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.900s	39.267us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.280s	67.910us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	17.850s	2.523ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	6.200s	432.346us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.230s	690.033us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.280s	67.910us	1	1	100.00
		spi_device_csr_aliasing	6.200s	432.346us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.580s	11.833us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.510s	111.673us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.790s	73.302us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.500s	6.409us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.550s	3.809us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	3.520s	355.589us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	3.520s	355.589us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.050s	1.258ms	1	1	100.00
		spi_device_tpm_sts_read	1.550s	89.218us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.640s	13.780us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	20.850s	99.303ms	1	1	100.00
		spi_device_flash_all	2.058m	106.530ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	8.330s	10.099ms	1	1	100.00
		spi_device_flash_all	2.058m	106.530ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	8.330s	10.099ms	1	1	100.00
		spi_device_flash_all	2.058m	106.530ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	2.058m	106.530ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	5.210s	360.374us	1	1	100.00
		spi_device_flash_all	2.058m	106.530ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	5.210s	360.374us	1	1	100.00
		spi_device_flash_all	2.058m	106.530ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	5.210s	360.374us	1	1	100.00
		spi_device_flash_all	2.058m	106.530ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	5.210s	360.374us	1	1	100.00
		spi_device_flash_all	2.058m	106.530ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	5.210s	360.374us	1	1	100.00
		spi_device_flash_all	2.058m	106.530ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	3.820s	1.331ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	12.560s	3.483ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	12.560s	3.483ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	12.560s	3.483ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	4.770s	184.280us	1	1	100.00
		spi_device_read_buffer_direct	5.160s	1.047ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	12.560s	3.483ms	1	1	100.00
		spi_device_flash_all	2.058m	106.530ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	2.058m	106.530ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	2.058m	106.530ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	4.960s	295.225us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	4.960s	295.225us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	4.843m	100.258ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.821m	74.452ms	1	1	100.00
V2	stress_all	spi_device_stress_all	5.647m	56.463ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.680s	23.114us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.610s	12.722us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.400s	41.106us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.400s	41.106us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.900s	39.267us	1	1	100.00
		spi_device_csr_rw	2.280s	67.910us	1	1	100.00
		spi_device_csr_aliasing	6.200s	432.346us	1	1	100.00
		spi_device_same_csr_outstanding	2.430s	130.485us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.900s	39.267us	1	1	100.00
		spi_device_csr_rw	2.280s	67.910us	1	1	100.00
		spi_device_csr_aliasing	6.200s	432.346us	1	1	100.00
		spi_device_same_csr_outstanding	2.430s	130.485us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.870s	695.356us	1	1	100.00
		spi_device_tl_intg_err	14.540s	315.410us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	14.540s	315.410us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	31.840s	3.983ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.79688843257114333333979707078437525869520289977580576579033944003612709168262
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   3848903 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[81])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   3848903 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   3848903 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[977])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.18555096246889305990929669348667816163936721514800121561527570264487582940152
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1546498 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc3c80d [110000111100100000001101] vs 0x0 [0])
        UVM_ERROR @   1632498 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x631018 [11000110001000000011000] vs 0x0 [0])
        UVM_ERROR @   1647498 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe4414c [111001000100000101001100] vs 0x0 [0])
        UVM_ERROR @   1687498 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xad7dbc [101011010111110110111100] vs 0x0 [0])
        UVM_ERROR @   1742498 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3247b3 [1100100100011110110011] vs 0x0 [0])