SPI_HOST Simulation Results

Wednesday June 18 2025 17:01:10 UTC

GitHub Revision: 952e1dd

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	30.000s	4.902ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	23.727us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	33.171us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	86.512us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	22.004us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	28.806us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	33.171us	1	1	100.00
		spi_host_csr_aliasing	3.000s	22.004us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	14.834us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	40.505us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	4.000s	22.108us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	5.000s	99.120us	1	1	100.00
		spi_host_error_cmd	3.000s	51.159us	1	1	100.00
		spi_host_event	6.000s	187.552us	1	1	100.00
V2	clock_rate	spi_host_speed	9.000s	290.313us	1	1	100.00
V2	speed	spi_host_speed	9.000s	290.313us	1	1	100.00
V2	chip_select_timing	spi_host_speed	9.000s	290.313us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	6.000s	126.621us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	29.385us	1	1	100.00
V2	cpol_cpha	spi_host_speed	9.000s	290.313us	1	1	100.00
V2	full_cycle	spi_host_speed	9.000s	290.313us	1	1	100.00
V2	duplex	spi_host_smoke	30.000s	4.902ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	30.000s	4.902ms	1	1	100.00
V2	stress_all	spi_host_stress_all	5.000s	231.046us	1	1	100.00
V2	spien	spi_host_spien	57.000s	5.416ms	1	1	100.00
V2	stall	spi_host_status_stall	1.167m	4.126ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	5.000s	475.674us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	5.000s	99.120us	1	1	100.00
V2	alert_test	spi_host_alert_test	3.000s	20.359us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	81.182us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	131.691us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	131.691us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	23.727us	1	1	100.00
		spi_host_csr_rw	3.000s	33.171us	1	1	100.00
		spi_host_csr_aliasing	3.000s	22.004us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	120.284us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	23.727us	1	1	100.00
		spi_host_csr_rw	3.000s	33.171us	1	1	100.00
		spi_host_csr_aliasing	3.000s	22.004us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	120.284us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	55.538us	1	1	100.00
		spi_host_sec_cm	4.000s	69.029us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	55.538us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	3.500m	9.004ms	1	1	100.00
		TOTAL			26	26	100.00