SRAM_CTRL/MAIN Simulation Results

Wednesday June 18 2025 17:01:10 UTC

GitHub Revision: 952e1dd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	31.350s	823.627us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.520s	18.204us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.670s	18.372us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.030s	255.703us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.610s	40.454us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.450s	700.906us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.670s	18.372us	1	1	100.00
		sram_ctrl_csr_aliasing	1.610s	40.454us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.960m	7.068ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	45.120s	1.995ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	6.397m	12.339ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.329m	12.521ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	8.209m	240.882ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	6.983m	9.810ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	50.280s	27.837ms	1	1	100.00
V2	executable	sram_ctrl_executable	6.838m	27.302ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	32.160s	3.403ms	1	1	100.00
		sram_ctrl_partial_access_b2b	7.558m	67.617ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	17.750s	2.870ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	15.030s	1.715ms	1	1	100.00
		sram_ctrl_throughput_w_readback	7.390s	2.850ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	5.968m	21.420ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.970s	1.350ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	46.905m	133.213ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.610s	48.317us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.710s	106.283us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.710s	106.283us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.520s	18.204us	1	1	100.00
		sram_ctrl_csr_rw	1.670s	18.372us	1	1	100.00
		sram_ctrl_csr_aliasing	1.610s	40.454us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.410s	18.004us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.520s	18.204us	1	1	100.00
		sram_ctrl_csr_rw	1.670s	18.372us	1	1	100.00
		sram_ctrl_csr_aliasing	1.610s	40.454us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.410s	18.004us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	16.010s	3.943ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.540s	8.553us	0	1	0.00
		sram_ctrl_tl_intg_err	2.750s	382.126us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.540s	8.553us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.750s	382.126us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	5.968m	21.420ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	5.968m	21.420ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.670s	18.372us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	6.838m	27.302ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	6.838m	27.302ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	6.838m	27.302ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	50.280s	27.837ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.100s	699.461us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	16.010s	3.943ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.990s	2.758ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	31.350s	823.627us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	31.350s	823.627us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	6.838m	27.302ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.540s	8.553us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	50.280s	27.837ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.540s	8.553us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.540s	8.553us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	31.350s	823.627us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.540s	8.553us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	14.990s	3.088ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.4103749496392733793173579375651123050245605545208991348217051766467777328126
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   8553231 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   8553231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---