SRAM_CTRL/RET Simulation Results

Wednesday June 18 2025 17:01:10 UTC

GitHub Revision: 952e1dd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 1.206m 137.321us 1 1 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 1.650s 49.267us 1 1 100.00
V1 csr_rw sram_ctrl_csr_rw 1.510s 17.992us 1 1 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.080s 31.104us 1 1 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 1.720s 41.301us 1 1 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 2.060s 134.353us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 1.510s 17.992us 1 1 100.00
sram_ctrl_csr_aliasing 1.720s 41.301us 1 1 100.00
V1 mem_walk sram_ctrl_mem_walk 10.870s 1.197ms 1 1 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 5.120s 709.020us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 multiple_keys sram_ctrl_multiple_keys 10.736m 45.930ms 1 1 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 1.863m 5.955ms 1 1 100.00
V2 bijection sram_ctrl_bijection 50.700s 3.866ms 1 1 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 7.550m 7.222ms 1 1 100.00
V2 lc_escalation sram_ctrl_lc_escalation 7.860s 1.923ms 1 1 100.00
V2 executable sram_ctrl_executable 9.899m 13.455ms 1 1 100.00
V2 partial_access sram_ctrl_partial_access 5.060s 67.085us 1 1 100.00
sram_ctrl_partial_access_b2b 2.151m 9.841ms 1 1 100.00
V2 max_throughput sram_ctrl_max_throughput 28.840s 184.710us 1 1 100.00
sram_ctrl_throughput_w_partial_write 31.990s 360.576us 1 1 100.00
sram_ctrl_throughput_w_readback 34.910s 1.201ms 1 1 100.00
V2 regwen sram_ctrl_regwen 10.647m 41.658ms 1 1 100.00
V2 ram_cfg sram_ctrl_ram_cfg 1.690s 54.970us 1 1 100.00
V2 stress_all sram_ctrl_stress_all 14.046m 133.295ms 1 1 100.00
V2 alert_test sram_ctrl_alert_test 1.530s 13.769us 1 1 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 3.690s 143.871us 1 1 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 3.690s 143.871us 1 1 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 1.650s 49.267us 1 1 100.00
sram_ctrl_csr_rw 1.510s 17.992us 1 1 100.00
sram_ctrl_csr_aliasing 1.720s 41.301us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.710s 43.686us 1 1 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 1.650s 49.267us 1 1 100.00
sram_ctrl_csr_rw 1.510s 17.992us 1 1 100.00
sram_ctrl_csr_aliasing 1.720s 41.301us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.710s 43.686us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 2.770s 873.818us 1 1 100.00
V2S tl_intg_err sram_ctrl_sec_cm 1.470s 1.344us 0 1 0.00
sram_ctrl_tl_intg_err 2.320s 97.568us 1 1 100.00
V2S prim_count_check sram_ctrl_sec_cm 1.470s 1.344us 0 1 0.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.320s 97.568us 1 1 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 10.647m 41.658ms 1 1 100.00
V2S sec_cm_readback_config_regwen sram_ctrl_regwen 10.647m 41.658ms 1 1 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 1.510s 17.992us 1 1 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 9.899m 13.455ms 1 1 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 9.899m 13.455ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 9.899m 13.455ms 1 1 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 7.860s 1.923ms 1 1 100.00
V2S sec_cm_prim_ram_ctrl_mubi sram_ctrl_mubi_enc_err 1.920s 495.583us 1 1 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 2.770s 873.818us 1 1 100.00
V2S sec_cm_mem_readback sram_ctrl_readback_err 2.110s 94.606us 1 1 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 1.206m 137.321us 1 1 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 1.206m 137.321us 1 1 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 9.899m 13.455ms 1 1 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 1.470s 1.344us 0 1 0.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 7.860s 1.923ms 1 1 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 1.470s 1.344us 0 1 0.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 1.470s 1.344us 0 1 0.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 1.206m 137.321us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 1.470s 1.344us 0 1 0.00
V2S TOTAL 4 5 80.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 3.135m 1.878ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 31 96.77

Failure Buckets