UART Simulation Results

Wednesday June 18 2025 17:01:10 UTC

GitHub Revision: 952e1dd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	7.640s	5.358ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.740s	104.773us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.570s	27.280us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.040s	75.049us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.410s	217.128us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.460s	16.840us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.570s	27.280us	1	1	100.00
		uart_csr_aliasing	1.410s	217.128us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	51.950s	96.402ms	1	1	100.00
V2	parity	uart_smoke	7.640s	5.358ms	1	1	100.00
		uart_tx_rx	51.950s	96.402ms	1	1	100.00
V2	parity_error	uart_intr	8.570s	25.090ms	1	1	100.00
		uart_rx_parity_err	24.250s	57.234ms	1	1	100.00
V2	watermark	uart_tx_rx	51.950s	96.402ms	1	1	100.00
		uart_intr	8.570s	25.090ms	1	1	100.00
V2	fifo_full	uart_fifo_full	3.299m	213.411ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.743m	89.444ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	24.950s	122.731ms	1	1	100.00
V2	rx_frame_err	uart_intr	8.570s	25.090ms	1	1	100.00
V2	rx_break_err	uart_intr	8.570s	25.090ms	1	1	100.00
V2	rx_timeout	uart_intr	8.570s	25.090ms	1	1	100.00
V2	perf	uart_perf	2.842m	21.036ms	1	1	100.00
V2	sys_loopback	uart_loopback	3.260s	1.564ms	1	1	100.00
V2	line_loopback	uart_loopback	3.260s	1.564ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	9.700s	19.020ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	6.340s	4.742ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	7.010s	1.257ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	4.480s	1.797ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	3.744m	128.546ms	1	1	100.00
V2	stress_all	uart_stress_all	3.874m	131.245ms	1	1	100.00
V2	alert_test	uart_alert_test	1.450s	14.203us	1	1	100.00
V2	intr_test	uart_intr_test	1.600s	25.980us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.740s	125.642us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.740s	125.642us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.740s	104.773us	1	1	100.00
		uart_csr_rw	1.570s	27.280us	1	1	100.00
		uart_csr_aliasing	1.410s	217.128us	1	1	100.00
		uart_same_csr_outstanding	1.460s	29.443us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.740s	104.773us	1	1	100.00
		uart_csr_rw	1.570s	27.280us	1	1	100.00
		uart_csr_aliasing	1.410s	217.128us	1	1	100.00
		uart_same_csr_outstanding	1.460s	29.443us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.630s	73.124us	1	1	100.00
		uart_tl_intg_err	1.780s	50.155us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.780s	50.155us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	10.090s	3.107ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.92484195001131153095434861636714743393724152752605602259929388002800156236436
      Line 70, in log /nightly/runs/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 17763615178 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0
        UVM_ERROR @ 17763656845 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 17763698512 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (149 [0x95] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 17835740755 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0
        UVM_ERROR @ 17835782422 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty