CHIP Simulation Results

Wednesday June 18 2025 17:01:10 UTC

GitHub Revision: `952e1dd`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	4.710m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	4.710m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	3.961m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	3.593m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	3.668m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.292m	5.618ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.292m	5.618ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.292m	5.618ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	26.750s	10.140us	0	1	0.00
		chip_sw_example_manufacturer	5.317m		0	1	0.00
		chip_sw_example_concurrency	4.295m	5.445ms	1	1	100.00
		chip_sw_uart_smoketest_signed	18.200s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	8.070s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	7.790s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	7.790s		0	1	0.00
V1	xbar_smoke	xbar_smoke	8.800s	12.829us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	4.536m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	9.460m	7.814ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.935m	5.002ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.314m		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	3.183m		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	3.585m		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	3.332m		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	4.200s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.200s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	4.851m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	4.632m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	4.731m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	4.731m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.996m	3.957ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.311m	3.028ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.433m	13.992ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.443s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	11.821s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	6.354m	9.745ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.041m	5.560ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	21.895m	18.016ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	21.895m	18.016ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	13.640s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.082m	5.805ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.082m	5.805ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.043m	18.024ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.963m	5.543ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	6.096m	5.837ms	1	1	100.00
		chip_sw_aes_idle	4.464m	4.183ms	1	1	100.00
		chip_sw_hmac_enc_idle	3.689m	4.055ms	1	1	100.00
		chip_sw_kmac_idle	3.385m	4.619ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	11.987m	12.022ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	11.462m	12.019ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	11.671m	12.016ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	12.710m	12.015ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	12.330s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	20.229s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	13.586s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.911s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	16.488s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.688s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.461s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	12.330s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	20.229s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	13.586s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.911s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	16.488s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.688s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.461s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	15.587s		0	1	0.00
		chip_sw_aes_enc_jitter_en	30.730s	10.300us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	34.760s	10.280us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	34.360s	10.100us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	35.110s	10.380us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.759s		0	1	0.00
		chip_sw_clkmgr_jitter	4.009m	5.503ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.424m	5.885ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	13.964s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	36.730s	10.100us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	41.820s	10.380us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	35.430s	10.320us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	37.200s	10.400us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	35.780s	10.140us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	13.895s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.205s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.488s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	11.589s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	17.394m	15.191ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	8.903m	17.301ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	6.082m	5.805ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	11.336s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	8.903m	17.301ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	25.364s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	16.366s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	11.620s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	23.210s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	10.816s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	17.394m	15.191ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.433m	13.992ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	21.585m	20.025ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	7.374m	5.531ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	8.131m	6.107ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.977m	3.577ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	17.394m	15.191ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	10.609s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	11.129s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	17.394m	15.191ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	12.424s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	8.131m	6.107ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	10.746s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	11.212s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.289s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	11.561s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	12.299s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	10.717s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	11.129s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	23.239s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	1.030m		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	23.239s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	23.239s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	23.239s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	6.272m	6.471ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	44.800s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	23.856s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	18.468s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	28.868s		0	1	0.00
		chip_sw_lc_ctrl_transition	23.239s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	6.867m	9.493ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	7.467m	12.931ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	12.696s		0	1	0.00
		chip_prim_tl_access	8.856m	12.844ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	12.330s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	20.229s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	13.586s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.911s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	16.488s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.688s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.461s		0	1	0.00
		chip_rv_dm_lc_disabled	6.354m	9.745ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.295m	5.070ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	30.730s	10.300us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.936m	5.906ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.464m	4.183ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.121m	5.376ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	34.760s	10.280us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.689m	4.055ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.269m	4.742ms	1	1	100.00
		chip_sw_kmac_mode_kmac	5.465m	5.473ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	35.110s	10.380us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	6.867m	9.493ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	23.239s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	28.160s	10.280us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	6.674m	5.941ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.385m	4.619ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	11.880s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	11.880s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	13.153s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.317m	4.588ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	12.961s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	6.867m	9.493ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	34.360s	10.100us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	21.792s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	15.587s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	6.096m	5.837ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	6.096m	5.837ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	6.096m	5.837ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	7.881m	5.629ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	7.467m	12.931ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	7.467m	12.931ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	7.653m	8.426ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.759s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	12.696s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	17.394m	15.191ms	1	1	100.00
		chip_sw_data_integrity_escalation	4.731m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	23.239s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	7.881m	5.629ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.867m	9.493ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	7.653m	8.426ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.440m	4.347ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	7.881m	5.629ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.867m	9.493ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	7.653m	8.426ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.440m	4.347ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	23.239s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	12.423s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	1.030m		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	44.800s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	23.856s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	18.468s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	28.868s		0	1	0.00
		chip_sw_lc_ctrl_transition	23.239s		0	1	0.00
		chip_prim_tl_access	8.856m	12.844ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	8.856m	12.844ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	41.860s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	20.392s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.205s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	15.587s		0	1	0.00
		chip_sw_aes_enc_jitter_en	30.730s	10.300us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	34.760s	10.280us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	34.360s	10.100us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	35.110s	10.380us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.759s		0	1	0.00
		chip_sw_clkmgr_jitter	4.009m	5.503ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	7.842m	6.295ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	7.842m	6.295ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	3.558m	3.169ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.186m	5.328ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	3.192m	4.113ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.046m	6.127ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	5.089m	4.409ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.098m	5.114ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.440m	4.347ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	21.585m	20.025ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	21.585m	20.025ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.588m	3.171ms	1	1	100.00
		chip_sw_aon_timer_smoketest	4.007m	6.023ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.528m	4.980ms	1	1	100.00
		chip_sw_csrng_smoketest	3.177m	3.651ms	1	1	100.00
		chip_sw_gpio_smoketest	4.215m	4.701ms	1	1	100.00
		chip_sw_hmac_smoketest	3.657m	6.275ms	1	1	100.00
		chip_sw_kmac_smoketest	3.501m	5.309ms	1	1	100.00
		chip_sw_otbn_smoketest	5.742m	5.792ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.603m	3.953ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.788m	3.719ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.232m	6.396ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.003m	4.493ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.150m	3.804ms	1	1	100.00
		chip_sw_uart_smoketest	3.141m	3.608ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	34.842s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	18.200s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	4.536m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	16.278s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.493m	4.056ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.448m	3.862ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.926m	5.607ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.208m	6.266ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	13.100s		0	1	0.00
		chip_rv_dm_lc_disabled	6.354m	9.745ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	17.918s		0	1	0.00
		chip_sw_lc_walkthrough_prod	13.007s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	11.540s		0	1	0.00
		chip_sw_lc_walkthrough_rma	1.137m		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	13.100s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	19.703s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	14.717s		0	1	0.00
		rom_volatile_raw_unlock	10.997s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	10.522s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	4.452m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	4.190m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.714m	4.313ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.714m	4.313ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	7.790s		0	1	0.00
		chip_same_csr_outstanding	13.120s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	7.790s		0	1	0.00
		chip_same_csr_outstanding	13.120s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	1.436m	76.355us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.670s	13.585us	1	1	100.00
		xbar_smoke_large_delays	3.753m	1.994ms	1	1	100.00
		xbar_smoke_slow_rsp	5.046m	2.020ms	1	1	100.00
		xbar_random_zero_delays	29.190s	26.493us	1	1	100.00
		xbar_random_large_delays	12.230m	6.639ms	1	1	100.00
		xbar_random_slow_rsp	22.926m	8.760ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	29.250s	17.439us	1	1	100.00
		xbar_error_and_unmapped_addr	38.560s	27.357us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	36.890s	42.268us	1	1	100.00
		xbar_error_and_unmapped_addr	38.560s	27.357us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.564m	354.379us	1	1	100.00
		xbar_access_same_device_slow_rsp	45.980m	18.528ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	39.020s	38.563us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	9.383m	564.265us	1	1	100.00
		xbar_stress_all_with_error	5.776m	428.860us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	18.913m	2.933ms	1	1	100.00
		xbar_stress_all_with_reset_error	10.902m	551.180us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	12.525s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	13.968s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	12.132s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	12.750s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	12.085s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	11.880s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.777s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	11.298s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.021s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	13.283s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	11.911s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	12.124s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	11.557s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	11.911s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	12.287s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	12.590s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	12.007s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	11.479s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	11.925s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	12.310s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	12.488s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.846s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	11.701s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	12.387s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	12.562s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	12.687s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	11.900s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.486s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.099s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	11.574s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	11.805s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	12.291s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.266s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.730s		0	1	0.00
		rom_e2e_asm_init_dev	11.297s		0	1	0.00
		rom_e2e_asm_init_prod	11.167s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.137s		0	1	0.00
		rom_e2e_asm_init_rma	11.289s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.730s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.215s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	11.087s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.340s		0	1	0.00
V2		TOTAL			65	205	31.71
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.419m	5.494ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.480m	5.085ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.323s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.656s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.746s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	14.338s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	17.394m	15.191ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	15.220s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	18.129m	15.659ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	14.406s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	12.036s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.323s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.656s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.746s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.196s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.898s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.213s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	55.484s		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	17.753m	12.722ms	1	1	100.00
		chip_plic_all_irqs_0	7.760m	5.532ms	1	1	100.00
		chip_plic_all_irqs_10	8.934m	7.377ms	1	1	100.00
		chip_sw_dma_inline_hashing	5.148m	5.572ms	1	1	100.00
		chip_sw_dma_abort	3.948m	4.239ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.960s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.293s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.345s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.832s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.743s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	12.611s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.594s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	10.804s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.171s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	10.620s		0	1	0.00
		chip_sw_mbx_smoketest	4.485m	5.994ms	1	1	100.00
		TOTAL			76	247	30.77

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.47398965789839397750724735650116458658470524160993904347007660021999942896284
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (7a036e)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 303.823s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.86634689512591591939614709432215739262932090612034117135329381057734436968564
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (aa7c6f)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 273.354s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.75071772018790303140544123722090105951317899609024409690321519338342420932399
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (0a463e)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 280.867s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.90316621321862142556256755747590513027664706408703280405326422599483309820346
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (59c4ab)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 267.782s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.14990415725407348587689432746334020592635563745955572809519790176712941583592
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (a02db2)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 272.242s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.5717998822543603301855342993645532009923914400723501370410512477162547947500
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.25231540528854593586851931599798200312019012012360547112439084335534479286411
    Line 412, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.33100480767069369379220020277401969546233496501734661341843866240636110408059
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.64475278388744331014189720052865216704027633140338562791933671286459780069869
    Line 410, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.39555697730920766866123483001807144897784194693343182546242778032802187182439
    Line 414, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 4 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.104978029068636697289162696060355316400659662351815010129456102225364541599341
Line 445, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12021.588100 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12021.588100 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.33906073066806282706575077731669418108273132115469638863295354139728259118315
Line 447, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12019.255291 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12019.255291 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.18740999612882021194561031952198160298777169500294959156902048445290725283514
Line 440, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12016.054023 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12016.054023 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.6043115914900463775491405674862903838137627004986849180490443204564626429396
Line 445, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12015.024964 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12015.024964 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.63784267702747249691552545524506195002797903299756796832208604602369807015561
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.56689415008391591134085914000566871823309744782034074761915168817815601415632
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.27399471217820299839184947457773792732991035851178625744285643943625214859653
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.19904940381198471892039837567280410058059692649257490797206946200946341171681
Line 507, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20024.658923 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20024.658923 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.58482269052406327703077306846946148903315265299665169004653644232646952397050
Line 504, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18016.048079 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18016.048079 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.46931367267751729957528117793244422692008497840311056607932947276823839426640
Line 484, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18024.424383 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18024.424383 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.97294161073704689625579895405994310746725951435294644003130680701389831275097
Line 470, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 9492.822120 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (96812697769414228481636912115757059405517695501072282208263742646675611637083 [0xd60a0b8c4f3dc9e6ba181817bdd9cdbe3910ab58c83a876a15949ed73130d55b] vs 3567703480329652138435989316554193058017807685500607128088230523315335049166 [0x7e33fa4ee40d3407df213daa316978ddaf7b7542907d641b1b3f035dc5dafce])
  UVM_INFO @ 9492.822120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.17254764325426857819995495192612864125277501911544142217543972558627325798029
Line 459, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 6470.752806 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (8433021848256552367474274607005743203624491882459373062128278588370694121766 [0x12a4ebd51597b4cd8a6b9aeb6f9626c67a6192beb9d5fb80a49d299353872926] vs 77924682979167823059295644744495854722361662148994105407489020342679132896501 [0xac47cebdf78b270475712e5e730264812aaf0054063ab8beedb2b41b9ae2fcf5])
  UVM_INFO @ 6470.752806 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.24983630605875122540652746167855687865453586456288232442389212849417458635100
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3956.940285 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: 'h30480000  a_data: 'h47e80e49  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hf  a_opcode: 'h1  a_user: 'h248b1  d_param: 'h0  d_source: 'hf  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3956.940285 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.30771386241072513538428542987933171745179805747817998521710329353839025071847
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3028.104004 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: 'h30480000  a_data: 'h4085a545  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h23  a_opcode: 'h1  a_user: 'h248df  d_param: 'h0  d_source: 'h23  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3028.104004 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.51941441980801986895450979642339628374966060874492048887618710818422735053455
    Line 788, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.83488124664509236685368247366787076480932053484558365464868403208903854975278
    Line 536, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5002.445640 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5002.445640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.72086115759805595796536005452439900564657013702538894707497623491852187008696
    Line 721, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 6106.876480 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 6106.876480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.82859774689516064521083163047459480363399566163261871884951984624118737810047
    Line 501, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 3168.967260 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 3168.967260 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.85857115859282296525366493160682430048088334220186633527782201485082930333532
    Line 479, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 5327.565910 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 5327.565910 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.63542841493086644704908964450982651716679307421947960452890291796238045807466
    Line 472, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 5804.540870 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 5804.540870 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.40462287529035977401213577087115854120032207679046646220381428932877810716381
    Line 434, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 6127.493928 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 6127.493928 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.17664723211277503822836189719944496613685238074088893498966339579928419061830
    Line 431, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@35782) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.12599475308808723190521323908443292099206336949339884500202880959510974156297
Line 254, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 4312.636360 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@35782) { a_addr: 'h1465112  a_data: 'he3f62378  a_mask: 'h4  a_size: 'h1  a_param: 'h0  a_source: 'ha2  a_opcode: 'h4  a_user: 'h27001  d_param: 'h0  d_source: 'ha2  d_data: 'h0  d_size: 'h1  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'h12a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4312.636360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.19322469807407235650908515874295547525346640631888077204501502866021423985368
    Line 402, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 13991.889256 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 13991.889256 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.1706548184165701558958053344152750966668946539113659436447021970052910021709
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 96
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.24338832531814621901442884401480305287412553417465450481241052040811367510733
    Line 426, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 4239.011708 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4239.011708 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```