DMA Simulation Results

Thursday June 19 2025 17:07:03 UTC

GitHub Revision: 83f35b5

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	8.000s	6.955ms	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	8.000s	2.094ms	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	11.000s	624.672us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	17.551us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	29.983us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	14.000s	672.283us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	9.000s	1.002ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	5.000s	98.130us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	29.983us	1	1	100.00
		dma_csr_aliasing	9.000s	1.002ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.067m	14.014ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	1.467m	7.752ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	3.100m	16.933ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	8.133m	50.325ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	1.467m	7.752ms	1	1	100.00
V2	dma_abort	dma_abort	23.000s	2.053ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	4.033m	140.024ms	1	1	100.00
V2	intr_test	dma_intr_test	3.000s	23.449us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	5.000s	89.725us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	5.000s	89.725us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	17.551us	1	1	100.00
		dma_csr_rw	4.000s	29.983us	1	1	100.00
		dma_csr_aliasing	9.000s	1.002ms	1	1	100.00
		dma_same_csr_outstanding	4.000s	55.691us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	17.551us	1	1	100.00
		dma_csr_rw	4.000s	29.983us	1	1	100.00
		dma_csr_aliasing	9.000s	1.002ms	1	1	100.00
		dma_same_csr_outstanding	4.000s	55.691us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	25.000s	143.128us	1	1	100.00
		dma_generic_stress	8.133m	50.325ms	1	1	100.00
		dma_handshake_stress	1.467m	7.752ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	6.000s	368.561us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	40.000s	4.532ms	1	1	100.00
		dma_longer_transfer	12.000s	2.047ms	1	1	100.00
		TOTAL			21	21	100.00