EDN Simulation Results

Thursday June 19 2025 17:07:03 UTC

GitHub Revision: 83f35b5

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.850s 29.086us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.880s 33.900us 1 1 100.00
V1 csr_rw edn_csr_rw 1.590s 37.675us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 5.650s 1.442ms 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 2.130s 33.960us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.980s 15.414us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.590s 37.675us 1 1 100.00
edn_csr_aliasing 2.130s 33.960us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.990s 36.593us 1 1 100.00
V2 csrng_commands edn_genbits 1.990s 36.593us 1 1 100.00
V2 genbits edn_genbits 1.990s 36.593us 1 1 100.00
V2 interrupts edn_intr 1.950s 28.508us 1 1 100.00
V2 alerts edn_alert 2.000s 186.966us 1 1 100.00
V2 errs edn_err 1.880s 19.063us 1 1 100.00
V2 disable edn_disable 1.700s 24.897us 1 1 100.00
edn_disable_auto_req_mode 2.310s 41.695us 1 1 100.00
V2 stress_all edn_stress_all 2.890s 272.453us 1 1 100.00
V2 intr_test edn_intr_test 1.590s 29.906us 1 1 100.00
V2 alert_test edn_alert_test 1.570s 47.448us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.400s 178.517us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 3.400s 178.517us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.880s 33.900us 1 1 100.00
edn_csr_rw 1.590s 37.675us 1 1 100.00
edn_csr_aliasing 2.130s 33.960us 1 1 100.00
edn_same_csr_outstanding 1.720s 23.962us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.880s 33.900us 1 1 100.00
edn_csr_rw 1.590s 37.675us 1 1 100.00
edn_csr_aliasing 2.130s 33.960us 1 1 100.00
edn_same_csr_outstanding 1.720s 23.962us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 7.960s 605.554us 1 1 100.00
edn_tl_intg_err 3.390s 128.221us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.790s 19.257us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 2.000s 186.966us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 7.960s 605.554us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 7.960s 605.554us 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 7.960s 605.554us 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 7.960s 605.554us 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.000s 186.966us 1 1 100.00
edn_sec_cm 7.960s 605.554us 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.000s 186.966us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.390s 128.221us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets