HMAC Simulation Results

Thursday June 19 2025 17:07:03 UTC

GitHub Revision: 83f35b5

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 2.700s 53.276us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.440s 25.058us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.570s 18.984us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 7.470s 218.655us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 6.570s 1.012ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.670s 126.988us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.570s 18.984us 1 1 100.00
hmac_csr_aliasing 6.570s 1.012ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 1.113m 1.476ms 1 1 100.00
V2 back_pressure hmac_back_pressure 48.480s 5.555ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.059m 5.920ms 1 1 100.00
hmac_test_sha384_vectors 20.180s 251.067us 1 1 100.00
hmac_test_sha512_vectors 19.610s 552.972us 1 1 100.00
hmac_test_hmac256_vectors 6.740s 194.587us 1 1 100.00
hmac_test_hmac384_vectors 10.160s 2.351ms 1 1 100.00
hmac_test_hmac512_vectors 8.500s 1.277ms 1 1 100.00
V2 burst_wr hmac_burst_wr 19.520s 5.104ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 3.628m 1.781ms 1 1 100.00
V2 error hmac_error 6.740s 2.391ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.009m 21.849ms 1 1 100.00
V2 save_and_restore hmac_smoke 2.700s 53.276us 1 1 100.00
hmac_long_msg 1.113m 1.476ms 1 1 100.00
hmac_back_pressure 48.480s 5.555ms 1 1 100.00
hmac_datapath_stress 3.628m 1.781ms 1 1 100.00
hmac_burst_wr 19.520s 5.104ms 1 1 100.00
hmac_stress_all 16.727m 28.419ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 2.700s 53.276us 1 1 100.00
hmac_long_msg 1.113m 1.476ms 1 1 100.00
hmac_back_pressure 48.480s 5.555ms 1 1 100.00
hmac_datapath_stress 3.628m 1.781ms 1 1 100.00
hmac_wipe_secret 1.009m 21.849ms 1 1 100.00
hmac_test_sha256_vectors 3.059m 5.920ms 1 1 100.00
hmac_test_sha384_vectors 20.180s 251.067us 1 1 100.00
hmac_test_sha512_vectors 19.610s 552.972us 1 1 100.00
hmac_test_hmac256_vectors 6.740s 194.587us 1 1 100.00
hmac_test_hmac384_vectors 10.160s 2.351ms 1 1 100.00
hmac_test_hmac512_vectors 8.500s 1.277ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 2.700s 53.276us 1 1 100.00
hmac_long_msg 1.113m 1.476ms 1 1 100.00
hmac_back_pressure 48.480s 5.555ms 1 1 100.00
hmac_datapath_stress 3.628m 1.781ms 1 1 100.00
hmac_burst_wr 19.520s 5.104ms 1 1 100.00
hmac_error 6.740s 2.391ms 1 1 100.00
hmac_wipe_secret 1.009m 21.849ms 1 1 100.00
hmac_test_sha256_vectors 3.059m 5.920ms 1 1 100.00
hmac_test_sha384_vectors 20.180s 251.067us 1 1 100.00
hmac_test_sha512_vectors 19.610s 552.972us 1 1 100.00
hmac_test_hmac256_vectors 6.740s 194.587us 1 1 100.00
hmac_test_hmac384_vectors 10.160s 2.351ms 1 1 100.00
hmac_test_hmac512_vectors 8.500s 1.277ms 1 1 100.00
hmac_stress_all 16.727m 28.419ms 1 1 100.00
V2 stress_all hmac_stress_all 16.727m 28.419ms 1 1 100.00
V2 alert_test hmac_alert_test 1.380s 13.496us 1 1 100.00
V2 intr_test hmac_intr_test 1.470s 12.657us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.120s 121.466us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.120s 121.466us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.440s 25.058us 1 1 100.00
hmac_csr_rw 1.570s 18.984us 1 1 100.00
hmac_csr_aliasing 6.570s 1.012ms 1 1 100.00
hmac_same_csr_outstanding 1.840s 100.598us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.440s 25.058us 1 1 100.00
hmac_csr_rw 1.570s 18.984us 1 1 100.00
hmac_csr_aliasing 6.570s 1.012ms 1 1 100.00
hmac_same_csr_outstanding 1.840s 100.598us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 2.140s 350.293us 1 1 100.00
hmac_tl_intg_err 3.210s 164.449us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.210s 164.449us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 2.700s 53.276us 1 1 100.00
V3 stress_reset hmac_stress_reset 3.670s 666.621us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 35.200s 2.282ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.720s 134.900us 1 1 100.00
TOTAL 28 28 100.00