I2C Simulation Results

Thursday June 19 2025 17:07:03 UTC

GitHub Revision: `83f35b5`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	53.530s	7.286ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	9.090s	763.370us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.570s	26.139us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.630s	55.377us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.800s	229.424us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.560s	110.997us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.540s	28.931us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.630s	55.377us	1	1	100.00
		i2c_csr_aliasing	2.560s	110.997us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.640s	78.235us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	1.629m	6.223ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	30.420s	2.891ms	1	1	100.00
V2	host_override	i2c_host_override	1.540s	18.290us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.478m	5.372ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	24.530s	3.214ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.660s	76.125us	1	1	100.00
		i2c_host_fifo_fmt_empty	5.560s	1.570ms	1	1	100.00
		i2c_host_fifo_reset_rx	3.250s	2.214ms	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	31.400s	1.800ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	23.920s	772.008us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.850s	125.465us	0	1	0.00
V2	target_glitch	i2c_target_glitch	6.370s	4.016ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	16.085m	58.799ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	5.260s	823.380us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	38.620s	4.516ms	1	1	100.00
		i2c_target_intr_smoke	6.060s	1.209ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.700s	205.447us	1	1	100.00
		i2c_target_fifo_reset_tx	2.010s	760.946us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	10.054m	53.971ms	1	1	100.00
		i2c_target_stress_rd	38.620s	4.516ms	1	1	100.00
		i2c_target_intr_stress_wr	10.170s	12.228ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.380s	1.299ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	14.560s	10.012ms	0	1	0.00
V2	bad_address	i2c_target_bad_addr	4.110s	969.644us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	22.370s	10.027ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.900s	526.374us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.330s	235.995us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	30.420s	2.891ms	1	1	100.00
		i2c_host_perf_precise	29.310s	1.685ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	23.920s	772.008us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	5.550s	440.776us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.720s	1.777ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.600s	455.568us	1	1	100.00
		i2c_target_nack_txstretch	2.060s	533.547us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	3.800s	270.875us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.930s	1.913ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.400s	81.908us	1	1	100.00
V2	intr_test	i2c_intr_test	1.560s	45.841us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.920s	350.387us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.920s	350.387us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.570s	26.139us	1	1	100.00
		i2c_csr_rw	1.630s	55.377us	1	1	100.00
		i2c_csr_aliasing	2.560s	110.997us	1	1	100.00
		i2c_same_csr_outstanding	1.690s	57.457us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.570s	26.139us	1	1	100.00
		i2c_csr_rw	1.630s	55.377us	1	1	100.00
		i2c_csr_aliasing	2.560s	110.997us	1	1	100.00
		i2c_same_csr_outstanding	1.690s	57.457us	1	1	100.00
V2		TOTAL			34	38	89.47
V2S	tl_intg_err	i2c_tl_intg_err	2.650s	124.791us	1	1	100.00
		i2c_sec_cm	1.850s	172.103us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.650s	124.791us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	33.480s	962.484us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.900s	247.240us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	7.000s	504.148us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			43	50	86.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.96802749707799336257909471513154495707175121631775362920927530046867160788652
    Line 88, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 962484113 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 962484113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.89419588869531271065266110284324573561924060737094416266988786437612895339203
    Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 504148059 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 504148059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.50334942458450282775794580684617943407119002182084073077493875589806102708206
Line 122, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 6222885629 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @1222806

UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 1 failures:
- Test i2c_target_stretch has 1 failures.
  - 0.i2c_target_stretch.47052793192540329061309334001186289111585688676497125539620027507565684541287
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10012245577 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10012245577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.113488151011663993545376785622394100209903340385006720859350219473589424025680
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 247239669 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 211 [0xd3])
  UVM_INFO @ 247239669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 0.i2c_target_hrst.79619870136501884610906402802487085891028092123233625803245013133765289683931
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10026842703 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10026842703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 0.i2c_host_mode_toggle.54365537880410913006138767910975726008388376065091824964606420791968191526327
    Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
```
  UVM_ERROR @ 125465124 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------
```