KEYMGR Simulation Results

Thursday June 19 2025 17:07:03 UTC

GitHub Revision: `83f35b5`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	3.230s	113.003us	1	1	100.00
V1	random	keymgr_random	5.710s	858.685us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.180s	318.947us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	2.090s	14.434us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	5.250s	514.523us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	2.440s	175.497us	0	1	0.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.530s	122.989us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.090s	14.434us	1	1	100.00
		keymgr_csr_aliasing	2.440s	175.497us	0	1	0.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	4.010s	82.272us	1	1	100.00
V2	sideload	keymgr_sideload	10.700s	425.011us	1	1	100.00
		keymgr_sideload_kmac	4.470s	729.301us	1	1	100.00
		keymgr_sideload_aes	5.980s	204.239us	1	1	100.00
		keymgr_sideload_otbn	3.130s	593.585us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.920s	56.203us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.610s	100.152us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	4.010s	409.756us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	3.960s	2.259ms	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	2.490s	225.155us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	3.200s	561.047us	1	1	100.00
V2	stress_all	keymgr_stress_all	22.350s	898.310us	1	1	100.00
V2	intr_test	keymgr_intr_test	1.790s	11.871us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.510s	13.919us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.130s	183.585us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.130s	183.585us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.180s	318.947us	1	1	100.00
		keymgr_csr_rw	2.090s	14.434us	1	1	100.00
		keymgr_csr_aliasing	2.440s	175.497us	0	1	0.00
		keymgr_same_csr_outstanding	2.730s	109.424us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.180s	318.947us	1	1	100.00
		keymgr_csr_rw	2.090s	14.434us	1	1	100.00
		keymgr_csr_aliasing	2.440s	175.497us	0	1	0.00
		keymgr_same_csr_outstanding	2.730s	109.424us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	5.320s	437.117us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	5.320s	437.117us	1	1	100.00
		keymgr_tl_intg_err	3.660s	406.769us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.920s	1.403ms	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.920s	1.403ms	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.920s	1.403ms	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.920s	1.403ms	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	2.180s	64.001us	0	1	0.00
V2S	prim_count_check	keymgr_sec_cm	5.320s	437.117us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	5.320s	437.117us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	3.660s	406.769us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.920s	1.403ms	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	4.010s	82.272us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	5.710s	858.685us	1	1	100.00
		keymgr_csr_rw	2.090s	14.434us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	5.710s	858.685us	1	1	100.00
		keymgr_csr_rw	2.090s	14.434us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	5.710s	858.685us	1	1	100.00
		keymgr_csr_rw	2.090s	14.434us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.610s	100.152us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	2.490s	225.155us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	2.490s	225.155us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	5.710s	858.685us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.960s	109.628us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	5.320s	437.117us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	5.320s	437.117us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	5.320s	437.117us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	4.550s	658.441us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.610s	100.152us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	5.320s	437.117us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	5.320s	437.117us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	5.320s	437.117us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	4.550s	658.441us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	4.550s	658.441us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	5.320s	437.117us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	4.550s	658.441us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	5.320s	437.117us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	4.550s	658.441us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	12.190s	3.223ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			27	30	90.00

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

Test keymgr_shadow_reg_errors_with_csr_rw has 1 failures.

0.keymgr_shadow_reg_errors_with_csr_rw.46108449545187184917168349267666647408671411059530206428664710928113688891622
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[5] & 'hffffffff)))'
  UVM_ERROR @  64000755 ps: (keymgr_csr_assert_fpv.sv:400) [ASSERT FAILED] sealing_sw_binding_0_rd_A
  UVM_INFO @  64000755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_csr_aliasing has 1 failures.

0.keymgr_csr_aliasing.61476308916019948519155968294738159049637633478693898148351738036750006061454
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[10] & 'hffffffff)))'
  UVM_ERROR @ 175496617 ps: (keymgr_csr_assert_fpv.sv:430) [ASSERT FAILED] sealing_sw_binding_5_rd_A
  UVM_INFO @ 175496617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 0.keymgr_stress_all_with_rand_reset.76926897462211867073704980155515048227217003725439580465175208112182884033543
    Line 1864, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3223235060 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3223235060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```