KMAC/MASKED Simulation Results

Thursday June 19 2025 17:07:03 UTC

GitHub Revision: 83f35b5

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	43.020s	3.318ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.050s	21.171us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.960s	110.917us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.580s	6.921ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.790s	787.935us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.810s	34.331us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.960s	110.917us	1	1	100.00
		kmac_csr_aliasing	6.790s	787.935us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.770s	14.897us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.240s	49.151us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	28.392m	224.874ms	1	1	100.00
V2	burst_write	kmac_burst_write	13.773m	20.656ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	33.920s	12.923ms	1	1	100.00
		kmac_test_vectors_sha3_256	32.139m	633.650ms	1	1	100.00
		kmac_test_vectors_sha3_384	20.670s	977.129us	1	1	100.00
		kmac_test_vectors_sha3_512	17.955m	49.518ms	1	1	100.00
		kmac_test_vectors_shake_128	33.750m	72.315ms	1	1	100.00
		kmac_test_vectors_shake_256	30.253m	123.152ms	1	1	100.00
		kmac_test_vectors_kmac	4.090s	340.469us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.600s	244.816us	1	1	100.00
V2	sideload	kmac_sideload	1.462m	6.119ms	1	1	100.00
V2	app	kmac_app	4.327m	13.333ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.140m	30.749ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.616m	5.729ms	1	1	100.00
V2	error	kmac_error	2.580s	85.278us	1	1	100.00
V2	key_error	kmac_key_error	3.690s	1.575ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.850s	59.785us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.730s	54.401us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	2.190s	48.427us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	12.660s	6.098ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.330s	41.249us	1	1	100.00
V2	stress_all	kmac_stress_all	17.040m	80.873ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.810s	109.982us	1	1	100.00
V2	alert_test	kmac_alert_test	1.580s	54.926us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.720s	89.007us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.720s	89.007us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.050s	21.171us	1	1	100.00
		kmac_csr_rw	1.960s	110.917us	1	1	100.00
		kmac_csr_aliasing	6.790s	787.935us	1	1	100.00
		kmac_same_csr_outstanding	2.440s	278.084us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.050s	21.171us	1	1	100.00
		kmac_csr_rw	1.960s	110.917us	1	1	100.00
		kmac_csr_aliasing	6.790s	787.935us	1	1	100.00
		kmac_same_csr_outstanding	2.440s	278.084us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.350s	147.758us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.350s	147.758us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.350s	147.758us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.350s	147.758us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.920s	64.026us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	28.380s	2.719ms	1	1	100.00
		kmac_tl_intg_err	5.320s	1.077ms	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.320s	1.077ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.330s	41.249us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	43.020s	3.318ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.462m	6.119ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.350s	147.758us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	28.380s	2.719ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	28.380s	2.719ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	28.380s	2.719ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	43.020s	3.318ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.330s	41.249us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	28.380s	2.719ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	46.160s	3.087ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	43.020s	3.318ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.447m	10.134ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.53445330072875316251712721964483529396618838488111380021369530789582667812046
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
        UVM_ERROR @  64026429 ps: (kmac_csr_assert_fpv.sv:512) [ASSERT FAILED] prefix_2_rd_A
        UVM_INFO @  64026429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---