83f35b5| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 5.770s | 1.634ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 1.650s | 59.514us | 1 | 1 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 2.060s | 22.134us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 7.880s | 744.029us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 4.210s | 204.786us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 3.070s | 92.067us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 2.060s | 22.134us | 1 | 1 | 100.00 |
| kmac_csr_aliasing | 4.210s | 204.786us | 1 | 1 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 1.620s | 9.794us | 1 | 1 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.940s | 103.559us | 1 | 1 | 100.00 |
| V1 | TOTAL | 8 | 8 | 100.00 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 9.494m | 59.222ms | 1 | 1 | 100.00 |
| V2 | burst_write | kmac_burst_write | 10.917m | 132.398ms | 1 | 1 | 100.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 27.405m | 92.203ms | 1 | 1 | 100.00 |
| kmac_test_vectors_sha3_256 | 24.659m | 721.424ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 19.840s | 2.266ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 9.373m | 18.493ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_shake_128 | 1.544m | 2.260ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_shake_256 | 4.285m | 23.378ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_kmac | 2.880s | 123.884us | 1 | 1 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 3.090s | 291.239us | 1 | 1 | 100.00 | ||
| V2 | sideload | kmac_sideload | 4.378m | 132.550ms | 1 | 1 | 100.00 |
| V2 | app | kmac_app | 1.237m | 9.500ms | 1 | 1 | 100.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 18.670s | 5.582ms | 1 | 1 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 1.020m | 4.541ms | 1 | 1 | 100.00 |
| V2 | error | kmac_error | 3.982m | 16.611ms | 1 | 1 | 100.00 |
| V2 | key_error | kmac_key_error | 1.890s | 435.298us | 1 | 1 | 100.00 |
| V2 | sideload_invalid | kmac_sideload_invalid | 49.390s | 10.233ms | 0 | 1 | 0.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 24.050s | 506.434us | 1 | 1 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 9.190s | 691.985us | 1 | 1 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 34.870s | 13.503ms | 1 | 1 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 1.930s | 63.110us | 1 | 1 | 100.00 |
| V2 | stress_all | kmac_stress_all | 4.637m | 21.205ms | 1 | 1 | 100.00 |
| V2 | intr_test | kmac_intr_test | 1.650s | 19.750us | 1 | 1 | 100.00 |
| V2 | alert_test | kmac_alert_test | 1.740s | 23.505us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 3.040s | 103.144us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 3.040s | 103.144us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.650s | 59.514us | 1 | 1 | 100.00 |
| kmac_csr_rw | 2.060s | 22.134us | 1 | 1 | 100.00 | ||
| kmac_csr_aliasing | 4.210s | 204.786us | 1 | 1 | 100.00 | ||
| kmac_same_csr_outstanding | 2.320s | 413.726us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.650s | 59.514us | 1 | 1 | 100.00 |
| kmac_csr_rw | 2.060s | 22.134us | 1 | 1 | 100.00 | ||
| kmac_csr_aliasing | 4.210s | 204.786us | 1 | 1 | 100.00 | ||
| kmac_same_csr_outstanding | 2.320s | 413.726us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 25 | 26 | 96.15 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 2.010s | 40.151us | 1 | 1 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 2.010s | 40.151us | 1 | 1 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 2.010s | 40.151us | 1 | 1 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 2.010s | 40.151us | 1 | 1 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 2.800s | 530.110us | 1 | 1 | 100.00 |
| V2S | tl_intg_err | kmac_sec_cm | 34.840s | 3.776ms | 1 | 1 | 100.00 |
| kmac_tl_intg_err | 3.860s | 492.034us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 3.860s | 492.034us | 1 | 1 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 1.930s | 63.110us | 1 | 1 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 5.770s | 1.634ms | 1 | 1 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 4.378m | 132.550ms | 1 | 1 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 2.010s | 40.151us | 1 | 1 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 34.840s | 3.776ms | 1 | 1 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 34.840s | 3.776ms | 1 | 1 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 34.840s | 3.776ms | 1 | 1 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 5.770s | 1.634ms | 1 | 1 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 1.930s | 63.110us | 1 | 1 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 34.840s | 3.776ms | 1 | 1 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 1.173m | 21.318ms | 1 | 1 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 5.770s | 1.634ms | 1 | 1 | 100.00 |
| V2S | TOTAL | 5 | 5 | 100.00 | |||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 12.570s | 1.810ms | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 38 | 40 | 95.00 |
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 1 failures:
0.kmac_sideload_invalid.41434214399893000771879095161775905980846123155629060558730040233888287093263
Line 91, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10232765282 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc3f7f000, Comparison=CompareOpEq, exp_data=0x1, call_count=18)
UVM_INFO @ 10232765282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
0.kmac_stress_all_with_rand_reset.25165816896307167223208327168085513397987845355501866427974359919267789497977
Line 116, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1809685452 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
UVM_INFO @ 1809685452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---