ROM_CTRL/64KB Simulation Results

Thursday June 19 2025 17:07:03 UTC

GitHub Revision: 83f35b5

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 7.880s 1.840ms 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 7.890s 209.397us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.010s 426.170us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 8.280s 299.027us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.140s 567.854us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 7.640s 569.913us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.010s 426.170us 1 1 100.00
rom_ctrl_csr_aliasing 7.140s 567.854us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.430s 1.410ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5.760s 955.743us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 6.760s 1.006ms 1 1 100.00
V2 stress_all rom_ctrl_stress_all 26.890s 13.602ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 13.020s 7.093ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 7.240s 297.997us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.280s 1.308ms 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.280s 1.308ms 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 7.890s 209.397us 1 1 100.00
rom_ctrl_csr_rw 6.010s 426.170us 1 1 100.00
rom_ctrl_csr_aliasing 7.140s 567.854us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.720s 728.246us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 7.890s 209.397us 1 1 100.00
rom_ctrl_csr_rw 6.010s 426.170us 1 1 100.00
rom_ctrl_csr_aliasing 7.140s 567.854us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.720s 728.246us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.874m 17.648ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 20.170s 756.162us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.579m 1.001ms 1 1 100.00
rom_ctrl_tl_intg_err 1.090m 673.791us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.579m 1.001ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.579m 1.001ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.874m 17.648ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.874m 17.648ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.874m 17.648ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.874m 17.648ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.874m 17.648ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.579m 1.001ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.579m 1.001ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 7.880s 1.840ms 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 7.880s 1.840ms 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 7.880s 1.840ms 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.090m 673.791us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.874m 17.648ms 1 1 100.00
rom_ctrl_kmac_err_chk 13.020s 7.093ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.874m 17.648ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.874m 17.648ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.874m 17.648ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 20.170s 756.162us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.579m 1.001ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.986m 16.149ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00