| V1 |
random |
rv_timer_random |
1.490s |
43.971us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
rv_timer_csr_hw_reset |
1.530s |
90.780us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
rv_timer_csr_rw |
1.490s |
52.443us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
rv_timer_csr_bit_bash |
3.230s |
181.749us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
rv_timer_csr_aliasing |
1.560s |
54.934us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
rv_timer_csr_mem_rw_with_rand_reset |
1.580s |
88.106us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
rv_timer_csr_rw |
1.490s |
52.443us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.560s |
54.934us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
random_reset |
rv_timer_random_reset |
1.510s |
49.393us |
1 |
1 |
100.00 |
| V2 |
disabled |
rv_timer_disabled |
1.660s |
281.432us |
1 |
1 |
100.00 |
| V2 |
cfg_update_on_fly |
rv_timer_cfg_update_on_fly |
1.579m |
90.665ms |
1 |
1 |
100.00 |
| V2 |
no_interrupt_test |
rv_timer_cfg_update_on_fly |
1.579m |
90.665ms |
1 |
1 |
100.00 |
| V2 |
stress |
rv_timer_stress_all |
2.340s |
1.418ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
rv_timer_alert_test |
1.400s |
11.385us |
1 |
1 |
100.00 |
| V2 |
intr_test |
rv_timer_intr_test |
1.480s |
12.571us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
rv_timer_tl_errors |
1.890s |
45.807us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
rv_timer_tl_errors |
1.890s |
45.807us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
rv_timer_csr_hw_reset |
1.530s |
90.780us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
1.490s |
52.443us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.560s |
54.934us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
1.520s |
58.498us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
rv_timer_csr_hw_reset |
1.530s |
90.780us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
1.490s |
52.443us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.560s |
54.934us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
1.520s |
58.498us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2S |
tl_intg_err |
rv_timer_sec_cm |
1.690s |
39.427us |
1 |
1 |
100.00 |
|
|
rv_timer_tl_intg_err |
1.860s |
182.207us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
rv_timer_tl_intg_err |
1.860s |
182.207us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
min_value |
rv_timer_min |
1.400s |
29.431us |
1 |
1 |
100.00 |
| V3 |
max_value |
rv_timer_max |
1.540s |
60.460us |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
rv_timer_stress_all_with_rand_reset |
35.090s |
4.251ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
3 |
3 |
100.00 |
|
|
TOTAL |
|
|
19 |
19 |
100.00 |