SPI_DEVICE/1R1W Simulation Results

Thursday June 19 2025 17:07:03 UTC

GitHub Revision: 83f35b5

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	16.890s	1.081ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.020s	193.067us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.910s	380.105us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	8.960s	739.379us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	14.870s	690.790us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.250s	107.052us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.910s	380.105us	1	1	100.00
		spi_device_csr_aliasing	14.870s	690.790us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.580s	10.332us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.010s	61.705us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.730s	128.516us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.540s	6.288us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.750s	5.685us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.730s	25.217us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.730s	25.217us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	6.340s	1.027ms	1	1	100.00
		spi_device_tpm_sts_read	1.630s	158.337us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	4.910s	2.098ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	4.880s	2.321ms	1	1	100.00
		spi_device_flash_all	1.590s	155.112us	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	8.450s	1.223ms	1	1	100.00
		spi_device_flash_all	1.590s	155.112us	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	8.450s	1.223ms	1	1	100.00
		spi_device_flash_all	1.590s	155.112us	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.590s	155.112us	1	1	100.00
V2	cmd_read_status	spi_device_intercept	13.610s	3.990ms	1	1	100.00
		spi_device_flash_all	1.590s	155.112us	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	13.610s	3.990ms	1	1	100.00
		spi_device_flash_all	1.590s	155.112us	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	13.610s	3.990ms	1	1	100.00
		spi_device_flash_all	1.590s	155.112us	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	13.610s	3.990ms	1	1	100.00
		spi_device_flash_all	1.590s	155.112us	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	13.610s	3.990ms	1	1	100.00
		spi_device_flash_all	1.590s	155.112us	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	4.500s	631.719us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	21.420s	7.105ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	21.420s	7.105ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	21.420s	7.105ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	9.720s	1.499ms	1	1	100.00
		spi_device_read_buffer_direct	3.650s	83.871us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	21.420s	7.105ms	1	1	100.00
		spi_device_flash_all	1.590s	155.112us	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.590s	155.112us	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.590s	155.112us	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.770s	372.682us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.770s	372.682us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	16.890s	1.081ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	4.732m	76.982ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.058m	20.522ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.700s	16.233us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.620s	13.906us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.390s	908.798us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.390s	908.798us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.020s	193.067us	1	1	100.00
		spi_device_csr_rw	1.910s	380.105us	1	1	100.00
		spi_device_csr_aliasing	14.870s	690.790us	1	1	100.00
		spi_device_same_csr_outstanding	2.430s	120.519us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.020s	193.067us	1	1	100.00
		spi_device_csr_rw	1.910s	380.105us	1	1	100.00
		spi_device_csr_aliasing	14.870s	690.790us	1	1	100.00
		spi_device_same_csr_outstanding	2.430s	120.519us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.330s	87.608us	1	1	100.00
		spi_device_tl_intg_err	16.440s	3.381ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	16.440s	3.381ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	3.192m	217.927ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.6025956039113692415935121711436108642014222248089876225319233956263941440705
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   5287892 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[45])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   5287892 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   5287892 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[941])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.94023353319100180184944056435183633416162994623286626271078128670730513220425
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3219128 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x324c58 [1100100100110001011000] vs 0x0 [0])
        UVM_ERROR @   3304128 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc473d0 [110001000111001111010000] vs 0x0 [0])
        UVM_ERROR @   3308128 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6c7a05 [11011000111101000000101] vs 0x0 [0])
        UVM_ERROR @   3354128 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa21639 [101000100001011000111001] vs 0x0 [0])
        UVM_ERROR @   3401128 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x12fd3f [100101111110100111111] vs 0x0 [0])