SRAM_CTRL/MAIN Simulation Results

Thursday June 19 2025 17:07:03 UTC

GitHub Revision: 83f35b5

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	39.190s	4.552ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.580s	15.944us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.690s	60.434us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.870s	144.043us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.540s	35.141us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.740s	706.928us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.690s	60.434us	1	1	100.00
		sram_ctrl_csr_aliasing	1.540s	35.141us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	2.984m	8.214ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.890m	41.410ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	12.600m	72.982ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.593m	17.600ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	18.955m	23.327ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	8.491m	45.898ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.265m	43.462ms	1	1	100.00
V2	executable	sram_ctrl_executable	1.510m	5.155ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	17.140s	3.131ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.278m	49.159ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	7.800s	2.440ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	40.450s	3.172ms	1	1	100.00
		sram_ctrl_throughput_w_readback	42.980s	2.714ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	6.398m	2.757ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.220s	641.131us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	10.311m	75.967ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.890s	23.648us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.380s	22.561us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.380s	22.561us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.580s	15.944us	1	1	100.00
		sram_ctrl_csr_rw	1.690s	60.434us	1	1	100.00
		sram_ctrl_csr_aliasing	1.540s	35.141us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.740s	25.292us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.580s	15.944us	1	1	100.00
		sram_ctrl_csr_rw	1.690s	60.434us	1	1	100.00
		sram_ctrl_csr_aliasing	1.540s	35.141us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.740s	25.292us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	27.800s	7.104ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.810s	3.115us	0	1	0.00
		sram_ctrl_tl_intg_err	2.480s	119.814us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.810s	3.115us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.480s	119.814us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	6.398m	2.757ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	6.398m	2.757ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.690s	60.434us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	1.510m	5.155ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	1.510m	5.155ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	1.510m	5.155ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.265m	43.462ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.130s	2.328ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	27.800s	7.104ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	6.450s	854.870us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	39.190s	4.552ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	39.190s	4.552ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	1.510m	5.155ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.810s	3.115us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.265m	43.462ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.810s	3.115us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.810s	3.115us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	39.190s	4.552ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.810s	3.115us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	6.340s	487.484us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.17835002507883205950300318685345863929060011502852681307486915337337712497283
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   3115484 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   3115484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---