SRAM_CTRL/RET Simulation Results

Thursday June 19 2025 17:07:03 UTC

GitHub Revision: 83f35b5

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	44.140s	577.868us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.580s	13.058us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.720s	13.420us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.330s	123.676us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.690s	43.413us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.410s	54.028us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.720s	13.420us	1	1	100.00
		sram_ctrl_csr_aliasing	1.690s	43.413us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.470s	457.858us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.120s	654.089us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	5.130m	5.639ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.315m	23.832ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	54.040s	16.845ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.593m	6.220ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	6.700s	623.020us	1	1	100.00
V2	executable	sram_ctrl_executable	12.618m	15.694ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	12.850s	620.797us	1	1	100.00
		sram_ctrl_partial_access_b2b	4.605m	18.859ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	34.640s	447.906us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	8.880s	1.056ms	1	1	100.00
		sram_ctrl_throughput_w_readback	3.270s	95.149us	1	1	100.00
V2	regwen	sram_ctrl_regwen	5.021m	92.666ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.690s	55.127us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	11.733m	18.212ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.560s	51.385us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.030s	290.523us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.030s	290.523us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.580s	13.058us	1	1	100.00
		sram_ctrl_csr_rw	1.720s	13.420us	1	1	100.00
		sram_ctrl_csr_aliasing	1.690s	43.413us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.560s	26.592us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.580s	13.058us	1	1	100.00
		sram_ctrl_csr_rw	1.720s	13.420us	1	1	100.00
		sram_ctrl_csr_aliasing	1.690s	43.413us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.560s	26.592us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.890s	1.653ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.500s	4.619us	0	1	0.00
		sram_ctrl_tl_intg_err	3.160s	201.213us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.500s	4.619us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.160s	201.213us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	5.021m	92.666ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	5.021m	92.666ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.720s	13.420us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	12.618m	15.694ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	12.618m	15.694ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	12.618m	15.694ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	6.700s	623.020us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.100s	73.033us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.890s	1.653ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.670s	45.937us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	44.140s	577.868us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	44.140s	577.868us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	12.618m	15.694ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.500s	4.619us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	6.700s	623.020us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.500s	4.619us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.500s	4.619us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	44.140s	577.868us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.500s	4.619us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.361m	1.187ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.73457514848556552821184590707594621230209746271185312620148053571311480617194
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   4619017 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   4619017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---