UART Simulation Results

Thursday June 19 2025 17:07:03 UTC

GitHub Revision: 83f35b5

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	3.780s	476.418us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.800s	18.726us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.620s	14.516us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.150s	122.613us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.630s	125.139us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.560s	181.809us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.620s	14.516us	1	1	100.00
		uart_csr_aliasing	1.630s	125.139us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	17.360s	25.188ms	1	1	100.00
V2	parity	uart_smoke	3.780s	476.418us	1	1	100.00
		uart_tx_rx	17.360s	25.188ms	1	1	100.00
V2	parity_error	uart_intr	4.596m	213.016ms	1	1	100.00
		uart_rx_parity_err	29.710s	110.630ms	1	1	100.00
V2	watermark	uart_tx_rx	17.360s	25.188ms	1	1	100.00
		uart_intr	4.596m	213.016ms	1	1	100.00
V2	fifo_full	uart_fifo_full	17.240s	37.318ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	25.850s	70.435ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	29.950s	18.645ms	1	1	100.00
V2	rx_frame_err	uart_intr	4.596m	213.016ms	1	1	100.00
V2	rx_break_err	uart_intr	4.596m	213.016ms	1	1	100.00
V2	rx_timeout	uart_intr	4.596m	213.016ms	1	1	100.00
V2	perf	uart_perf	1.410m	8.229ms	1	1	100.00
V2	sys_loopback	uart_loopback	3.060s	4.673ms	1	1	100.00
V2	line_loopback	uart_loopback	3.060s	4.673ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	28.360s	93.145ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	7.460s	27.030ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	3.410s	1.153ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	32.330s	5.455ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	6.665m	68.443ms	1	1	100.00
V2	stress_all	uart_stress_all	3.650s	7.029ms	0	1	0.00
V2	alert_test	uart_alert_test	1.960s	12.095us	1	1	100.00
V2	intr_test	uart_intr_test	1.760s	14.411us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.040s	24.234us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.040s	24.234us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.800s	18.726us	1	1	100.00
		uart_csr_rw	1.620s	14.516us	1	1	100.00
		uart_csr_aliasing	1.630s	125.139us	1	1	100.00
		uart_same_csr_outstanding	1.540s	93.042us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.800s	18.726us	1	1	100.00
		uart_csr_rw	1.620s	14.516us	1	1	100.00
		uart_csr_aliasing	1.630s	125.139us	1	1	100.00
		uart_same_csr_outstanding	1.540s	93.042us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	2.380s	174.008us	1	1	100.00
		uart_tl_intg_err	2.300s	504.105us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.300s	504.105us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	47.410s	9.733ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:
  • Test uart_stress_all has 1 failures.

    • 0.uart_stress_all.22022465355879150393983591345510045301269720118400207025053424964193514850231
      Line 71, in log /nightly/runs/scratch/master/uart-sim-vcs/0.uart_stress_all/latest/run.log

        UVM_ERROR @ 2201865750 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 2205490779 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 2213490843 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 2216199198 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 2264782920 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0