CHIP Simulation Results

Thursday June 19 2025 17:07:03 UTC

GitHub Revision: `83f35b5`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	3.364m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	3.364m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	2.081m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.777m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1.731m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.434m	4.367ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.434m	4.367ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.434m	4.367ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	27.510s	10.300us	0	1	0.00
		chip_sw_example_manufacturer	4.557m		0	1	0.00
		chip_sw_example_concurrency	4.514m	5.070ms	1	1	100.00
		chip_sw_uart_smoketest_signed	20.245s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	11.430s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	8.110s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	8.110s		0	1	0.00
V1	xbar_smoke	xbar_smoke	9.230s	12.884us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	2.850m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	10.015m	9.228ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	5.395m	5.142ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	1.293m		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	55.761s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	1.674m		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	1.371m		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.560s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.560s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	3.697m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	3.179m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	4.209m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	4.209m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.848m	3.240ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.339m	4.460ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.531m	15.094ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	13.244s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.643s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	10.369m	14.490ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.886m	5.388ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	18.832m	18.025ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	18.832m	18.025ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	12.325s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.268m	6.023ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.268m	6.023ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	6.819m	18.017ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.864m	4.938ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	4.994m	4.685ms	1	1	100.00
		chip_sw_aes_idle	3.936m	3.981ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.687m	4.239ms	1	1	100.00
		chip_sw_kmac_idle	3.880m	3.887ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	11.363m	12.023ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	12.608m	12.018ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	10.486m	12.027ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	11.330m	12.017ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	16.873s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.454s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.085s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.196s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	15.916s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.381s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.929s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	16.873s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.454s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.085s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.196s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	15.916s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.381s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.929s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	16.753s		0	1	0.00
		chip_sw_aes_enc_jitter_en	42.690s	10.220us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	33.450s	10.280us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	35.670s	10.240us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	34.580s	10.200us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.396s		0	1	0.00
		chip_sw_clkmgr_jitter	3.571m	3.745ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.778m	4.724ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	15.376s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	40.000s	10.100us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	39.150s	10.280us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	44.210s	10.160us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	36.010s	10.360us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	40.030s	10.200us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	11.877s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.348s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	15.614s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	11.506s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	19.000m	16.522ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	7.847m	12.427ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	5.268m	6.023ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	49.808s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	7.847m	12.427ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	36.970s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	15.826s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	21.787s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	13.589s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	15.801s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	19.000m	16.522ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.531m	15.094ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	23.239m	20.019ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	6.056m	5.494ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	8.425m	8.055ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.526m	3.545ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	19.000m	16.522ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	13.072s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	11.178s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	19.000m	16.522ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	11.743s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	8.425m	8.055ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	10.762s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	13.758s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	13.829s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	10.744s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	13.946s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	11.449s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	11.178s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	15.941s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	16.568s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	15.941s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	15.941s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	15.941s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	6.441m	9.458ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	14.721s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	11.158s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	12.684s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	14.173s		0	1	0.00
		chip_sw_lc_ctrl_transition	15.941s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	6.685m	6.447ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	9.437m	13.996ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	12.417s		0	1	0.00
		chip_prim_tl_access	6.436m	7.927ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	16.873s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.454s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.085s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.196s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	15.916s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.381s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.929s		0	1	0.00
		chip_rv_dm_lc_disabled	10.369m	14.490ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.375m	3.748ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	42.690s	10.220us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.596m	5.296ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.936m	3.981ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.521m	5.315ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	33.450s	10.280us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.687m	4.239ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.713m	5.773ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.636m	4.223ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	34.580s	10.200us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	6.685m	6.447ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	15.941s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	27.690s	10.340us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.506m	4.287ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.880m	3.887ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.109s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.109s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	12.140s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.906m	5.980ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	12.053s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	6.685m	6.447ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	35.670s	10.240us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	30.484s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	16.753s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	4.994m	4.685ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	4.994m	4.685ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	4.994m	4.685ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.230m	5.469ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.437m	13.996ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.437m	13.996ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	7.059m	8.586ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.396s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	12.417s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	19.000m	16.522ms	1	1	100.00
		chip_sw_data_integrity_escalation	4.209m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	15.941s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.230m	5.469ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.685m	6.447ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	7.059m	8.586ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.106m	4.408ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.230m	5.469ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.685m	6.447ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	7.059m	8.586ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.106m	4.408ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	15.941s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	10.272s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	16.568s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	14.721s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	11.158s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	12.684s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	14.173s		0	1	0.00
		chip_sw_lc_ctrl_transition	15.941s		0	1	0.00
		chip_prim_tl_access	6.436m	7.927ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	6.436m	7.927ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	14.845s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	11.050s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.348s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	16.753s		0	1	0.00
		chip_sw_aes_enc_jitter_en	42.690s	10.220us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	33.450s	10.280us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	35.670s	10.240us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	34.580s	10.200us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.396s		0	1	0.00
		chip_sw_clkmgr_jitter	3.571m	3.745ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	7.411m	8.296ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	7.411m	8.296ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	3.852m	5.185ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.111m	5.068ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.126m	5.103ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.118m	5.313ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.326m	5.129ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.837m	5.424ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.106m	4.408ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	23.239m	20.019ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	23.239m	20.019ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.668m	5.001ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.513m	5.878ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.579m	5.095ms	1	1	100.00
		chip_sw_csrng_smoketest	3.466m	3.296ms	1	1	100.00
		chip_sw_gpio_smoketest	3.809m	5.225ms	1	1	100.00
		chip_sw_hmac_smoketest	3.400m	4.801ms	1	1	100.00
		chip_sw_kmac_smoketest	3.368m	3.885ms	1	1	100.00
		chip_sw_otbn_smoketest	4.610m	6.228ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	4.013m	5.539ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.206m	3.532ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.429m	4.392ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.994m	5.143ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.802m	4.097ms	1	1	100.00
		chip_sw_uart_smoketest	3.177m	4.789ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	13.327s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	20.245s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.850m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	12.346s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.307m	3.741ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.847m	4.649ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.679m	5.425ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.806m	6.310ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	12.667s		0	1	0.00
		chip_rv_dm_lc_disabled	10.369m	14.490ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	19.843s		0	1	0.00
		chip_sw_lc_walkthrough_prod	24.254s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	25.121s		0	1	0.00
		chip_sw_lc_walkthrough_rma	20.942s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	12.667s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	11.827s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	15.294s		0	1	0.00
		rom_volatile_raw_unlock	15.662s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	31.907s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.542m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.801m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.349m	2.834ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.349m	2.834ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	8.110s		0	1	0.00
		chip_same_csr_outstanding	9.730s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	8.110s		0	1	0.00
		chip_same_csr_outstanding	9.730s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	1.793m	270.850us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.880s	11.140us	1	1	100.00
		xbar_smoke_large_delays	4.368m	2.085ms	1	1	100.00
		xbar_smoke_slow_rsp	4.776m	1.903ms	1	1	100.00
		xbar_random_zero_delays	1.296m	68.962us	1	1	100.00
		xbar_random_large_delays	9.291m	5.233ms	1	1	100.00
		xbar_random_slow_rsp	28.797m	11.232ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	49.170s	33.192us	1	1	100.00
		xbar_error_and_unmapped_addr	12.470s	9.717us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	2.644m	478.427us	1	1	100.00
		xbar_error_and_unmapped_addr	12.470s	9.717us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	3.240m	552.900us	1	1	100.00
		xbar_access_same_device_slow_rsp	36.556m	14.394ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	48.190s	51.945us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	6.239m	1.132ms	1	1	100.00
		xbar_stress_all_with_error	2.450m	167.794us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	13.519m	1.688ms	1	1	100.00
		xbar_stress_all_with_reset_error	5.020m	196.845us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	13.078s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	12.263s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	11.966s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	11.577s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	11.632s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	11.079s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.570s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	12.207s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	12.015s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	10.903s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	11.189s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	12.530s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	10.925s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	11.436s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	12.334s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	11.267s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	12.633s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	11.993s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	12.403s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	13.201s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	11.579s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	11.853s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	11.753s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	13.097s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	13.201s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	13.433s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.999s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.244s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.137s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	12.850s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	11.636s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	12.359s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.333s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.769s		0	1	0.00
		rom_e2e_asm_init_dev	12.406s		0	1	0.00
		rom_e2e_asm_init_prod	12.430s		0	1	0.00
		rom_e2e_asm_init_prod_end	13.135s		0	1	0.00
		rom_e2e_asm_init_rma	11.820s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.380s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.058s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	11.067s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.677s		0	1	0.00
V2		TOTAL			65	205	31.71
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.881m	4.171ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.016m	4.268ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.270s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.709s		0	1	0.00
		rom_e2e_jtag_debug_rma	10.917s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	15.318s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	19.000m	16.522ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	10.842s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	15.879m	13.935ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	11.725s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	11.927s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.270s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.709s		0	1	0.00
		rom_e2e_jtag_debug_rma	10.917s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.440s		0	1	0.00
		rom_e2e_jtag_inject_dev	10.989s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.552s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.370m		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	21.091m	15.987ms	1	1	100.00
		chip_plic_all_irqs_0	8.399m	7.383ms	1	1	100.00
		chip_plic_all_irqs_10	9.758m	6.691ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.300m	4.220ms	1	1	100.00
		chip_sw_dma_abort	3.803m	5.142ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	11.704s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.218s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.269s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.297s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.787s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	10.966s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.556s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.581s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.198s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.783s		0	1	0.00
		chip_sw_mbx_smoketest	4.000m	5.331ms	1	1	100.00
		TOTAL			76	247	30.77

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.80355003345209238460938899087874695769632459274617821105238158541631074569817
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (1 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (d449d7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 254.860s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.103697929462165197322018521704715170263219022159014007623118785752275438267393
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (ef9cad)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 241.851s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.108695886896795297296978466590634736799099050005845182595262705029376074677694
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (0f0c82)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 211.753s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.61103741432994931655220455715890257085147777708945670187920941070472785703701
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (e15a10)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 180.764s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.27150030893372309596391824515154294619739404059109246563944501671739824349527
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (60440b)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 191.848s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.55229743393308491901414263507956830497729959634973778685742601964718514439063
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.4741048588362778517548566537620444724980801462962442055570474972158807432174
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.80985337258863302202696031717263187127644207943884572306453006158364129578241
    Line 418, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.735356861555566797615837472269814609747568213961171090430487956398084868901
    Line 426, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.22672221228032488794580777393526492655196254082789215170977581730623260186396
    Line 412, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 4 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.9758177248608244142249612916423060487281942193495539377373715472829569472600
Line 509, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20018.611593 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20018.611593 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.54125348498580468968856727087907119509028382845686013147726793012844156208181
Line 473, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18025.226290 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18025.226290 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.60743440122457969301090605751820279375231716450769560659977869675917326059362
Line 465, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18016.503791 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18016.503791 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.38889515777682105802472664520632046378196466359635176096867540186857385371322
Line 440, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12016.671810 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12016.671810 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.89634255971067346625757065568145715211972797690571866108417238399481141650603
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.86850472902542615971233527794399125292632389349771988459108963070535900335817
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.38257659537596677931073929684524086220408928299221832242355942810098102253153
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.77980628306844964276184159339636721658397675729554276068054297803595715605154
Line 440, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12022.591165 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12022.591165 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.49175937407483673729232127212120442751069282608030704241059052664230736953309
Line 429, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12017.682062 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12017.682062 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.11860102834135070470130969794764870887656837488441220030546616221020329848515
Line 447, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12026.702258 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.702258 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.108528603004809071752552123114436595180338673097382198677104167923108526773785
Line 470, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 6447.016748 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (16085701817176416818567260937518757235226233261350510679075770398639758275582 [0x23902f412f171528b10fcd250e862494fd284e26989d080a72213827dce873fe] vs 8853860808041919219610434219859137331219275256431854265868436172339052170207 [0x13931b8daa4a25a83849999635f5ad1efb19df17cdcc10028334fed522be4bdf])
  UVM_INFO @ 6447.016748 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.52000329207357795046042088161546570067618810497203154357544398010716039838278
Line 466, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 9458.047080 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (72822825838578077109710145811200665257608858524882992841570513169531310444404 [0xa100423f1be2a03cbdb71043d9b047af02ae23fcedc071fad54eb62987980f74] vs 18949304853839891420734136298183090556454999244212645061008718709026155372627 [0x29e4ed2d26b11150bfe19684f456fb70bc85309938a729dabdb784a2351ba053])
  UVM_INFO @ 9458.047080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.100894925622849482556627963588958409019539968885743044719157508113356894447416
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3240.368846 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: 'h30480000  a_data: 'hc4470274  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hb  a_opcode: 'h1  a_user: 'h248f3  d_param: 'h0  d_source: 'hb  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3240.368846 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.14446738154988521490319648512147098941212571166438645373604705890585475913132
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4460.440061 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: 'h30480000  a_data: 'hd1f76f93  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h24  a_opcode: 'h0  a_user: 'h2694b  d_param: 'h0  d_source: 'h24  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4460.440061 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.53559676488462021648396337163501427720890858769156244145202660895545142966380
    Line 829, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.63013001787596932404315679233622160779378161044987177016577141748700647405729
    Line 475, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5141.716412 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5141.716412 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.96789730229784477847286901148472364613795548923994233997226635026770767192727
    Line 732, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 8054.692644 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 8054.692644 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.88252094799560663414750349644458199555266019481676680353749696505560999174335
    Line 468, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 5185.371354 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5185.371354 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.52603798170740755014052326554122450652203574520984261900457261794593446274391
    Line 449, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 5068.463762 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 5068.463762 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.11134755906846369401410447342326978702228817540054043476877992930355791921923
    Line 507, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 6023.127336 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 6023.127336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.4816803346966470189084416402798682576955892889950231617047080188929893942253
    Line 440, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5313.021944 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5313.021944 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.113148795874884623172311487477911137219969186682821903221793865123872665221282
    Line 430, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@36346) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.1195126445921824680197999915510346731776784634683441188440610269767825270447
Line 254, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2834.014630 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@36346) { a_addr: 'h2210  a_data: 'h21e7c27d  a_mask: 'h1  a_size: 'h1  a_param: 'h0  a_source: 'heb  a_opcode: 'h4  a_user: 'h260ef  d_param: 'h0  d_source: 'heb  d_data: 'h0  d_size: 'h1  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'h12a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2834.014630 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.37956965939561875272582465668682931160516527070710318014021395772442662425153
    Line 403, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 15093.524020 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 15093.524020 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.21791593313972189605865498118557598268187710628085242762919079597607237845909
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 96
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.114032863425083559853898751364040328125469105608645841661710741764275792275376
    Line 428, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 5142.137354 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 5142.137354 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```