DMA Simulation Results

Monday June 23 2025 17:05:19 UTC

GitHub Revision: cbe9098

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	7.000s	286.027us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	6.000s	809.883us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	7.000s	681.260us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	234.774us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	28.522us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	13.000s	1.609ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	9.000s	1.904ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	119.688us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	28.522us	1	1	100.00
		dma_csr_aliasing	9.000s	1.904ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	27.000s	3.116ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	5.000m	57.362ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	3.467m	17.633ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	15.217m	84.155ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	5.000m	57.362ms	1	1	100.00
V2	dma_abort	dma_abort	18.000s	2.124ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	4.567m	51.707ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	19.026us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	5.000s	172.370us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	5.000s	172.370us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	234.774us	1	1	100.00
		dma_csr_rw	4.000s	28.522us	1	1	100.00
		dma_csr_aliasing	9.000s	1.904ms	1	1	100.00
		dma_same_csr_outstanding	4.000s	55.900us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	234.774us	1	1	100.00
		dma_csr_rw	4.000s	28.522us	1	1	100.00
		dma_csr_aliasing	9.000s	1.904ms	1	1	100.00
		dma_same_csr_outstanding	4.000s	55.900us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	19.000s	201.486us	1	1	100.00
		dma_generic_stress	15.217m	84.155ms	1	1	100.00
		dma_handshake_stress	5.000m	57.362ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	5.000s	117.665us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	1.133m	13.203ms	1	1	100.00
		dma_longer_transfer	5.000s	162.594us	1	1	100.00
		TOTAL			21	21	100.00