EDN Simulation Results

Monday June 23 2025 17:05:19 UTC

GitHub Revision: cbe9098

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.870s	35.509us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.560s	84.356us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.750s	17.763us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.190s	377.219us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.840s	15.832us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.390s	23.226us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.750s	17.763us	1	1	100.00
		edn_csr_aliasing	1.840s	15.832us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.850s	64.211us	1	1	100.00
V2	csrng_commands	edn_genbits	1.850s	64.211us	1	1	100.00
V2	genbits	edn_genbits	1.850s	64.211us	1	1	100.00
V2	interrupts	edn_intr	1.840s	25.124us	1	1	100.00
V2	alerts	edn_alert	1.880s	101.709us	1	1	100.00
V2	errs	edn_err	1.790s	19.611us	1	1	100.00
V2	disable	edn_disable	1.600s	22.198us	1	1	100.00
		edn_disable_auto_req_mode	1.810s	104.324us	1	1	100.00
V2	stress_all	edn_stress_all	1.940s	69.886us	1	1	100.00
V2	intr_test	edn_intr_test	1.730s	40.133us	1	1	100.00
V2	alert_test	edn_alert_test	1.720s	21.083us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.090s	66.543us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.090s	66.543us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.560s	84.356us	1	1	100.00
		edn_csr_rw	1.750s	17.763us	1	1	100.00
		edn_csr_aliasing	1.840s	15.832us	1	1	100.00
		edn_same_csr_outstanding	1.780s	15.017us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.560s	84.356us	1	1	100.00
		edn_csr_rw	1.750s	17.763us	1	1	100.00
		edn_csr_aliasing	1.840s	15.832us	1	1	100.00
		edn_same_csr_outstanding	1.780s	15.017us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	4.040s	1.807ms	1	1	100.00
		edn_tl_intg_err	2.800s	278.695us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.900s	85.004us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.880s	101.709us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	4.040s	1.807ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	4.040s	1.807ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	4.040s	1.807ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	4.040s	1.807ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.880s	101.709us	1	1	100.00
		edn_sec_cm	4.040s	1.807ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.880s	101.709us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.800s	278.695us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	31.200s	3.667ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00