| V1 |
smoke |
hmac_smoke |
9.190s |
3.672ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
hmac_csr_hw_reset |
1.680s |
26.503us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
hmac_csr_rw |
1.810s |
29.853us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
hmac_csr_bit_bash |
7.450s |
251.453us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
hmac_csr_aliasing |
6.710s |
2.139ms |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
hmac_csr_mem_rw_with_rand_reset |
4.155m |
138.064ms |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
hmac_csr_rw |
1.810s |
29.853us |
1 |
1 |
100.00 |
|
|
hmac_csr_aliasing |
6.710s |
2.139ms |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
long_msg |
hmac_long_msg |
44.590s |
2.626ms |
1 |
1 |
100.00 |
| V2 |
back_pressure |
hmac_back_pressure |
53.160s |
5.207ms |
1 |
1 |
100.00 |
| V2 |
test_vectors |
hmac_test_sha256_vectors |
2.929m |
12.982ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha384_vectors |
6.365m |
24.985ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha512_vectors |
6.571m |
23.662ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac256_vectors |
6.860s |
226.733us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac384_vectors |
8.020s |
3.228ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac512_vectors |
8.650s |
1.436ms |
1 |
1 |
100.00 |
| V2 |
burst_wr |
hmac_burst_wr |
16.250s |
803.366us |
1 |
1 |
100.00 |
| V2 |
datapath_stress |
hmac_datapath_stress |
10.054m |
4.224ms |
1 |
1 |
100.00 |
| V2 |
error |
hmac_error |
28.390s |
600.515us |
1 |
1 |
100.00 |
| V2 |
wipe_secret |
hmac_wipe_secret |
4.740s |
1.320ms |
1 |
1 |
100.00 |
| V2 |
save_and_restore |
hmac_smoke |
9.190s |
3.672ms |
1 |
1 |
100.00 |
|
|
hmac_long_msg |
44.590s |
2.626ms |
1 |
1 |
100.00 |
|
|
hmac_back_pressure |
53.160s |
5.207ms |
1 |
1 |
100.00 |
|
|
hmac_datapath_stress |
10.054m |
4.224ms |
1 |
1 |
100.00 |
|
|
hmac_burst_wr |
16.250s |
803.366us |
1 |
1 |
100.00 |
|
|
hmac_stress_all |
12.106m |
32.655ms |
1 |
1 |
100.00 |
| V2 |
fifo_empty_status_interrupt |
hmac_smoke |
9.190s |
3.672ms |
1 |
1 |
100.00 |
|
|
hmac_long_msg |
44.590s |
2.626ms |
1 |
1 |
100.00 |
|
|
hmac_back_pressure |
53.160s |
5.207ms |
1 |
1 |
100.00 |
|
|
hmac_datapath_stress |
10.054m |
4.224ms |
1 |
1 |
100.00 |
|
|
hmac_wipe_secret |
4.740s |
1.320ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha256_vectors |
2.929m |
12.982ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha384_vectors |
6.365m |
24.985ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha512_vectors |
6.571m |
23.662ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac256_vectors |
6.860s |
226.733us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac384_vectors |
8.020s |
3.228ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac512_vectors |
8.650s |
1.436ms |
1 |
1 |
100.00 |
| V2 |
wide_digest_configurable_key_length |
hmac_smoke |
9.190s |
3.672ms |
1 |
1 |
100.00 |
|
|
hmac_long_msg |
44.590s |
2.626ms |
1 |
1 |
100.00 |
|
|
hmac_back_pressure |
53.160s |
5.207ms |
1 |
1 |
100.00 |
|
|
hmac_datapath_stress |
10.054m |
4.224ms |
1 |
1 |
100.00 |
|
|
hmac_burst_wr |
16.250s |
803.366us |
1 |
1 |
100.00 |
|
|
hmac_error |
28.390s |
600.515us |
1 |
1 |
100.00 |
|
|
hmac_wipe_secret |
4.740s |
1.320ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha256_vectors |
2.929m |
12.982ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha384_vectors |
6.365m |
24.985ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha512_vectors |
6.571m |
23.662ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac256_vectors |
6.860s |
226.733us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac384_vectors |
8.020s |
3.228ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac512_vectors |
8.650s |
1.436ms |
1 |
1 |
100.00 |
|
|
hmac_stress_all |
12.106m |
32.655ms |
1 |
1 |
100.00 |
| V2 |
stress_all |
hmac_stress_all |
12.106m |
32.655ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
hmac_alert_test |
1.550s |
115.269us |
1 |
1 |
100.00 |
| V2 |
intr_test |
hmac_intr_test |
1.530s |
13.008us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
hmac_tl_errors |
2.370s |
138.927us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
hmac_tl_errors |
2.370s |
138.927us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
hmac_csr_hw_reset |
1.680s |
26.503us |
1 |
1 |
100.00 |
|
|
hmac_csr_rw |
1.810s |
29.853us |
1 |
1 |
100.00 |
|
|
hmac_csr_aliasing |
6.710s |
2.139ms |
1 |
1 |
100.00 |
|
|
hmac_same_csr_outstanding |
2.890s |
737.566us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
hmac_csr_hw_reset |
1.680s |
26.503us |
1 |
1 |
100.00 |
|
|
hmac_csr_rw |
1.810s |
29.853us |
1 |
1 |
100.00 |
|
|
hmac_csr_aliasing |
6.710s |
2.139ms |
1 |
1 |
100.00 |
|
|
hmac_same_csr_outstanding |
2.890s |
737.566us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
17 |
17 |
100.00 |
| V2S |
tl_intg_err |
hmac_sec_cm |
2.050s |
41.665us |
1 |
1 |
100.00 |
|
|
hmac_tl_intg_err |
3.160s |
2.000ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
hmac_tl_intg_err |
3.160s |
2.000ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
write_config_and_secret_key_during_msg_wr |
hmac_smoke |
9.190s |
3.672ms |
1 |
1 |
100.00 |
| V3 |
stress_reset |
hmac_stress_reset |
3.450s |
1.375ms |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
hmac_stress_all_with_rand_reset |
1.138m |
9.478ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
2 |
2 |
100.00 |
|
Unmapped tests |
hmac_directed |
3.940s |
199.958us |
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
28 |
28 |
100.00 |