I2C Simulation Results

Monday June 23 2025 17:05:19 UTC

GitHub Revision: cbe9098

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	48.290s	3.684ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	19.280s	3.189ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.610s	98.148us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.610s	25.762us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.710s	67.016us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.840s	57.639us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.850s	78.856us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.610s	25.762us	1	1	100.00
		i2c_csr_aliasing	1.840s	57.639us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	3.710s	180.296us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	4.044m	12.770ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	58.560s	5.228ms	1	1	100.00
V2	host_override	i2c_host_override	1.610s	26.957us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	51.290s	6.128ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	52.480s	29.569ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.710s	457.621us	1	1	100.00
		i2c_host_fifo_fmt_empty	5.950s	352.678us	1	1	100.00
		i2c_host_fifo_reset_rx	7.190s	612.638us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	28.230s	7.131ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	25.650s	5.098ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.230s	58.175us	0	1	0.00
V2	target_glitch	i2c_target_glitch	7.650s	7.825ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	46.670s	35.288ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.950s	963.837us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	6.740s	1.589ms	1	1	100.00
		i2c_target_intr_smoke	7.760s	2.400ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.250s	173.414us	1	1	100.00
		i2c_target_fifo_reset_tx	2.120s	422.617us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	32.250s	38.517ms	1	1	100.00
		i2c_target_stress_rd	6.740s	1.589ms	1	1	100.00
		i2c_target_intr_stress_wr	41.850s	6.961ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.280s	3.830ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	53.080s	1.758ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	5.510s	1.382ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	3.100s	1.603ms	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.400s	580.952us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.230s	352.890us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	58.560s	5.228ms	1	1	100.00
		i2c_host_perf_precise	30.880s	5.947ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	25.650s	5.098ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	4.660s	388.150us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.740s	3.357ms	1	1	100.00
		i2c_target_nack_acqfull_addr	3.120s	2.721ms	1	1	100.00
		i2c_target_nack_txstretch	1.960s	396.397us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	21.250s	3.320ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	3.380s	558.362us	1	1	100.00
V2	alert_test	i2c_alert_test	1.550s	16.933us	1	1	100.00
V2	intr_test	i2c_intr_test	1.610s	49.931us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.820s	149.377us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.820s	149.377us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.610s	98.148us	1	1	100.00
		i2c_csr_rw	1.610s	25.762us	1	1	100.00
		i2c_csr_aliasing	1.840s	57.639us	1	1	100.00
		i2c_same_csr_outstanding	1.630s	84.182us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.610s	98.148us	1	1	100.00
		i2c_csr_rw	1.610s	25.762us	1	1	100.00
		i2c_csr_aliasing	1.840s	57.639us	1	1	100.00
		i2c_same_csr_outstanding	1.630s	84.182us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	2.040s	129.984us	1	1	100.00
		i2c_sec_cm	2.010s	69.144us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.040s	129.984us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	29.040s	3.385ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.460s	179.506us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	9.090s	748.476us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.106290700189531301572373250419740316010803845892230644862969515335534087029713
      Line 96, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3384696275 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3384696275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.110599168114867576651997565761083824923467048366640016098450491537556395654648
      Line 87, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 748476433 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 748476433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.88286999473396916581135582208703971604212006268302405152909300024862204554126
      Line 115, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 12770266017 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @2340784
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.92654337337323305355743131083470008229446732610893896840238110162528866648360
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 179506297 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 140 [0x8c])
        UVM_INFO @ 179506297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.36875075388194758872158302937175152524648738262949423738380899894259511391143
      Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @  58174500 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
        --> EXP:
        ---------------------------------------------------
        Name            Type                Size  Value
        ---------------------------------------------------
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.79493758488121951889420522918649058566652137595068663215187286779525576713211
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 396396745 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 396396745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---