KEYMGR Simulation Results

Monday June 23 2025 17:05:19 UTC

GitHub Revision: cbe9098

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	3.670s	96.785us	1	1	100.00
V1	random	keymgr_random	6.060s	476.086us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.770s	11.949us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	2.020s	19.825us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	5.900s	450.711us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	3.660s	270.203us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.390s	170.094us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.020s	19.825us	1	1	100.00
		keymgr_csr_aliasing	3.660s	270.203us	1	1	100.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	6.760s	604.693us	1	1	100.00
V2	sideload	keymgr_sideload	2.930s	215.355us	1	1	100.00
		keymgr_sideload_kmac	5.780s	2.400ms	1	1	100.00
		keymgr_sideload_aes	6.000s	444.042us	1	1	100.00
		keymgr_sideload_otbn	2.950s	221.561us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.830s	370.399us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	8.940s	392.125us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	4.510s	1.924ms	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	4.730s	196.645us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	3.370s	232.327us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	3.440s	582.663us	1	1	100.00
V2	stress_all	keymgr_stress_all	33.950s	7.475ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.580s	37.039us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.930s	13.368us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.720s	349.274us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.720s	349.274us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.770s	11.949us	1	1	100.00
		keymgr_csr_rw	2.020s	19.825us	1	1	100.00
		keymgr_csr_aliasing	3.660s	270.203us	1	1	100.00
		keymgr_same_csr_outstanding	2.080s	39.990us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.770s	11.949us	1	1	100.00
		keymgr_csr_rw	2.020s	19.825us	1	1	100.00
		keymgr_csr_aliasing	3.660s	270.203us	1	1	100.00
		keymgr_same_csr_outstanding	2.080s	39.990us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	10.170s	598.954us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	10.170s	598.954us	1	1	100.00
		keymgr_tl_intg_err	3.520s	480.851us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.050s	234.251us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.050s	234.251us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.050s	234.251us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.050s	234.251us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	1.850s	32.647us	0	1	0.00
V2S	prim_count_check	keymgr_sec_cm	10.170s	598.954us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	10.170s	598.954us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	3.520s	480.851us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.050s	234.251us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	6.760s	604.693us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	6.060s	476.086us	1	1	100.00
		keymgr_csr_rw	2.020s	19.825us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	6.060s	476.086us	1	1	100.00
		keymgr_csr_rw	2.020s	19.825us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	6.060s	476.086us	1	1	100.00
		keymgr_csr_rw	2.020s	19.825us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	8.940s	392.125us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	3.370s	232.327us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	3.370s	232.327us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	6.060s	476.086us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	19.290s	2.926ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	10.170s	598.954us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	10.170s	598.954us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	10.170s	598.954us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.510s	329.173us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	8.940s	392.125us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	10.170s	598.954us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	10.170s	598.954us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	10.170s	598.954us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.510s	329.173us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.510s	329.173us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	10.170s	598.954us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.510s	329.173us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	10.170s	598.954us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.510s	329.173us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	15.610s	333.236us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			28	30	93.33

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

  • Test keymgr_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.keymgr_shadow_reg_errors_with_csr_rw.29575122510862173982493711724454303927910841041152452172674678438712335412135
      Line 75, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[5] & 'hffffffff)))'
        UVM_ERROR @  32646907 ps: (keymgr_csr_assert_fpv.sv:400) [ASSERT FAILED] sealing_sw_binding_0_rd_A
        UVM_INFO @  32646907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.keymgr_csr_mem_rw_with_rand_reset.98079001564048098911300945993569924135761505323252508326267918849445383897957
      Line 86, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[16] & 'hffffffff)))'
        UVM_ERROR @ 170094247 ps: (keymgr_csr_assert_fpv.sv:466) [ASSERT FAILED] attest_sw_binding_3_rd_A
        UVM_INFO @ 170094247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---