| V1 |
smoke |
keymgr_dpe_smoke |
9.260s |
899.427us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
keymgr_dpe_csr_hw_reset |
1.700s |
45.792us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
keymgr_dpe_csr_rw |
1.770s |
14.931us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
keymgr_dpe_csr_bit_bash |
4.470s |
307.471us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
keymgr_dpe_csr_aliasing |
4.420s |
436.672us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
keymgr_dpe_csr_mem_rw_with_rand_reset |
2.140s |
18.037us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
keymgr_dpe_csr_rw |
1.770s |
14.931us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
4.420s |
436.672us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
intr_test |
keymgr_dpe_intr_test |
1.700s |
58.707us |
1 |
1 |
100.00 |
| V2 |
alert_test |
keymgr_dpe_alert_test |
1.720s |
159.332us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
keymgr_dpe_tl_errors |
2.800s |
139.904us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
keymgr_dpe_tl_errors |
2.800s |
139.904us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
keymgr_dpe_csr_hw_reset |
1.700s |
45.792us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.770s |
14.931us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
4.420s |
436.672us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
1.990s |
65.792us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
keymgr_dpe_csr_hw_reset |
1.700s |
45.792us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.770s |
14.931us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
4.420s |
436.672us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
1.990s |
65.792us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
4 |
4 |
100.00 |
| V2S |
tl_intg_err |
keymgr_dpe_sec_cm |
6.750s |
333.635us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_tl_intg_err |
3.900s |
204.900us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error |
keymgr_dpe_shadow_reg_errors |
3.310s |
112.203us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
keymgr_dpe_shadow_reg_errors |
3.310s |
112.203us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
keymgr_dpe_shadow_reg_errors |
3.310s |
112.203us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
keymgr_dpe_shadow_reg_errors |
3.310s |
112.203us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
keymgr_dpe_shadow_reg_errors_with_csr_rw |
4.160s |
345.675us |
1 |
1 |
100.00 |
| V2S |
prim_count_check |
keymgr_dpe_sec_cm |
6.750s |
333.635us |
1 |
1 |
100.00 |
| V2S |
prim_fsm_check |
keymgr_dpe_sec_cm |
6.750s |
333.635us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
4 |
4 |
100.00 |
|
|
TOTAL |
|
|
14 |
14 |
100.00 |