KMAC/MASKED Simulation Results

Monday June 23 2025 17:05:19 UTC

GitHub Revision: cbe9098

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	4.060s	2.056ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.740s	68.383us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.710s	16.080us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.290s	961.187us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.470s	263.198us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.100s	171.308us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.710s	16.080us	1	1	100.00
		kmac_csr_aliasing	7.470s	263.198us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.780s	26.406us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.880s	32.969us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	26.897m	82.037ms	1	1	100.00
V2	burst_write	kmac_burst_write	1.373m	4.186ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	31.630m	376.377ms	1	1	100.00
		kmac_test_vectors_sha3_256	22.575m	17.613ms	1	1	100.00
		kmac_test_vectors_sha3_384	21.300s	3.243ms	1	1	100.00
		kmac_test_vectors_sha3_512	19.330s	2.095ms	1	1	100.00
		kmac_test_vectors_shake_128	26.811m	81.558ms	1	1	100.00
		kmac_test_vectors_shake_256	21.743m	17.495ms	1	1	100.00
		kmac_test_vectors_kmac	2.850s	47.942us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.280s	163.323us	1	1	100.00
V2	sideload	kmac_sideload	3.801m	9.034ms	1	1	100.00
V2	app	kmac_app	25.430s	1.289ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.561m	8.586ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	41.020s	17.831ms	1	1	100.00
V2	error	kmac_error	2.996m	64.668ms	1	1	100.00
V2	key_error	kmac_key_error	4.960s	1.190ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.690s	45.532us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	34.770s	2.079ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.930s	21.752us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	58.670s	50.445ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	4.510s	159.268us	1	1	100.00
V2	stress_all	kmac_stress_all	18.047m	97.109ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.710s	33.295us	1	1	100.00
V2	alert_test	kmac_alert_test	1.840s	27.236us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.560s	266.739us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.560s	266.739us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.740s	68.383us	1	1	100.00
		kmac_csr_rw	1.710s	16.080us	1	1	100.00
		kmac_csr_aliasing	7.470s	263.198us	1	1	100.00
		kmac_same_csr_outstanding	2.460s	189.794us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.740s	68.383us	1	1	100.00
		kmac_csr_rw	1.710s	16.080us	1	1	100.00
		kmac_csr_aliasing	7.470s	263.198us	1	1	100.00
		kmac_same_csr_outstanding	2.460s	189.794us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.090s	92.384us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.090s	92.384us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.090s	92.384us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.090s	92.384us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.680s	47.445us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	1.021m	7.495ms	1	1	100.00
		kmac_tl_intg_err	3.010s	139.138us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.010s	139.138us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	4.510s	159.268us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	4.060s	2.056ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.801m	9.034ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.090s	92.384us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.021m	7.495ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.021m	7.495ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.021m	7.495ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	4.060s	2.056ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	4.510s	159.268us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.021m	7.495ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.750m	78.890ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	4.060s	2.056ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.013m	5.005ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.642234224200980241727464669463963877589106031216677265522726982819662605587
      Line 308, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5005044001 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 5005044001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---