KMAC/UNMASKED Simulation Results

Monday June 23 2025 17:05:19 UTC

GitHub Revision: cbe9098

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	25.370s	2.019ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.790s	30.844us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.910s	57.289us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.270s	580.797us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.570s	269.710us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.930s	256.814us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.910s	57.289us	1	1	100.00
		kmac_csr_aliasing	4.570s	269.710us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.670s	14.185us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.870s	61.581us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.357m	4.629ms	1	1	100.00
V2	burst_write	kmac_burst_write	1.500m	17.671ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	25.470s	2.542ms	1	1	100.00
		kmac_test_vectors_sha3_256	23.240s	601.915us	1	1	100.00
		kmac_test_vectors_sha3_384	20.800s	1.675ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.400s	11.699ms	1	1	100.00
		kmac_test_vectors_shake_128	2.424m	33.003ms	1	1	100.00
		kmac_test_vectors_shake_256	16.959m	322.994ms	1	1	100.00
		kmac_test_vectors_kmac	2.980s	218.535us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.460s	405.954us	1	1	100.00
V2	sideload	kmac_sideload	2.179m	8.595ms	1	1	100.00
V2	app	kmac_app	22.080s	24.270ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.983m	44.267ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	44.330s	6.548ms	1	1	100.00
V2	error	kmac_error	3.324m	7.387ms	1	1	100.00
V2	key_error	kmac_key_error	11.700s	1.651ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.450s	145.420us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	7.170s	486.554us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	25.140s	2.095ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	19.050s	2.289ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.400s	106.416us	1	1	100.00
V2	stress_all	kmac_stress_all	1.704m	27.253ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.620s	16.524us	1	1	100.00
V2	alert_test	kmac_alert_test	1.500s	56.654us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.170s	638.766us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.170s	638.766us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.790s	30.844us	1	1	100.00
		kmac_csr_rw	1.910s	57.289us	1	1	100.00
		kmac_csr_aliasing	4.570s	269.710us	1	1	100.00
		kmac_same_csr_outstanding	2.120s	96.172us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.790s	30.844us	1	1	100.00
		kmac_csr_rw	1.910s	57.289us	1	1	100.00
		kmac_csr_aliasing	4.570s	269.710us	1	1	100.00
		kmac_same_csr_outstanding	2.120s	96.172us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.390s	204.333us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.390s	204.333us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.390s	204.333us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.390s	204.333us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.920s	76.838us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	18.900s	1.777ms	1	1	100.00
		kmac_tl_intg_err	4.190s	275.648us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.190s	275.648us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.400s	106.416us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	25.370s	2.019ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.179m	8.595ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.390s	204.333us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	18.900s	1.777ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	18.900s	1.777ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	18.900s	1.777ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	25.370s	2.019ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.400s	106.416us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	18.900s	1.777ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	30.060s	2.742ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	25.370s	2.019ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.319m	19.186ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.83407295318389410747421861146759373073936223685329224447145944208910880760139
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
        UVM_ERROR @  76837749 ps: (kmac_csr_assert_fpv.sv:512) [ASSERT FAILED] prefix_2_rd_A
        UVM_INFO @  76837749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---