cbe9098| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 46.000s | 7.926ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 4.000s | 56.659us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 4.000s | 28.986us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 4.000s | 36.976us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 3.000s | 11.539us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 4.000s | 1.451us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 4.000s | 28.986us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 3.000s | 11.539us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | mbx_stress | mbx_stress | 35.000s | 2.330ms | 1 | 1 | 100.00 |
| mbx_stress_zero_delays | 49.000s | 1.071ms | 1 | 1 | 100.00 | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 40.000s | 4.279ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 7.000s | 22.751us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 5.000s | 3.224us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 5.000s | 3.224us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 4.000s | 56.659us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 28.986us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 3.000s | 11.539us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 3.000s | 13.043us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 4.000s | 56.659us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 28.986us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 3.000s | 11.539us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 3.000s | 13.043us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 6 | 83.33 | |||
| V2S | tl_intg_err | mbx_sec_cm | 7.000s | 34.658us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 4.000s | 16.178us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| TOTAL | 11 | 14 | 78.57 |
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutPartialData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_errors.24904497419047514330328536710281251917344247693604438471605679922752699973731
Line 82, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_ERROR @ 3224235 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x3f320eb3 a_data = 0x63d41e48 a_mask = 0x8 a_size = 0x3 a_param = 0x0 a_source = 0xc1 a_opcode = PutPartialData a_user = 0x24db8 d_data = 0x217f60e4 d_size = 0x3 d_param = 0x0 d_source = 0xb3 d_opcode = AccessAck d_error = 0 d_user = 11000011001100 d_sink = 0 req_abort_after_a_valid_len = 1 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 3224235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutFullData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_intg_err.68051127992769039668472762231440454873583551647421576604818769924260919148686
Line 92, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 16177827 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x1518a640 a_data = 0x1cbac0e8 a_mask = 0x3 a_size = 0x1 a_param = 0x0 a_source = 0x90 a_opcode = PutFullData a_user = 0x27e47 d_data = 0x81a51bfe d_size = 0x1 d_param = 0x0 d_source = 0xd2 d_opcode = AccessAckData d_error = 0 d_user = 10010011101010 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 16177827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutFullData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_csr_mem_rw_with_rand_reset.59967794998121962403555569952439244404496243734688080575288329797608778023511
Line 83, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 1451218 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xd27d0126 a_data = 0x3ef5e688 a_mask = 0x4 a_size = 0x1 a_param = 0x0 a_source = 0x15 a_opcode = PutFullData a_user = 0x253ff d_data = 0xed586396 d_size = 0x3 d_param = 0x0 d_source = 0xbe d_opcode = AccessAck d_error = 0 d_user = 1101000011100 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 1451218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---