OTBN Simulation Results

Monday June 23 2025 17:05:19 UTC

GitHub Revision: cbe9098

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	148.109us	1	1	100.00
V1	single_binary	otbn_single	9.000s	145.475us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	8.000s	25.930us	1	1	100.00
V1	csr_rw	otbn_csr_rw	7.000s	12.860us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	7.000s	105.316us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	13.049us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	26.930us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	12.860us	1	1	100.00
		otbn_csr_aliasing	6.000s	13.049us	1	1	100.00
V1	mem_walk	otbn_mem_walk	30.000s	6.609ms	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	9.000s	468.486us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	44.000s	667.402us	1	1	100.00
V2	multi_error	otbn_multi_err	51.000s	563.300us	1	1	100.00
V2	back_to_back	otbn_multi	46.000s	789.864us	1	1	100.00
V2	stress_all	otbn_stress_all	44.000s	646.973us	1	1	100.00
V2	lc_escalation	otbn_escalate	1.317m	360.873us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	23.443us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	8.000s	23.883us	1	1	100.00
V2	alert_test	otbn_alert_test	6.000s	219.806us	1	1	100.00
V2	intr_test	otbn_intr_test	6.000s	45.863us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	6.000s	57.621us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	6.000s	57.621us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	8.000s	25.930us	1	1	100.00
		otbn_csr_rw	7.000s	12.860us	1	1	100.00
		otbn_csr_aliasing	6.000s	13.049us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	14.404us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	8.000s	25.930us	1	1	100.00
		otbn_csr_rw	7.000s	12.860us	1	1	100.00
		otbn_csr_aliasing	6.000s	13.049us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	14.404us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	12.000s	29.375us	1	1	100.00
		otbn_dmem_err	9.000s	14.526us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	12.000s	105.855us	1	1	100.00
		otbn_controller_ispr_rdata_err	10.000s	206.818us	1	1	100.00
		otbn_mac_bignum_acc_err	31.000s	257.106us	1	1	100.00
		otbn_urnd_err	8.000s	97.134us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	10.318us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	62.881us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	7.000s	132.558us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	7.000s	9.620us	0	1	0.00
		otbn_tl_intg_err	20.000s	421.092us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	19.000s	100.803us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	7.000s	9.620us	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	7.000s	9.620us	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	148.109us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	9.000s	14.526us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	12.000s	29.375us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	20.000s	421.092us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	1.317m	360.873us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	12.000s	29.375us	1	1	100.00
		otbn_dmem_err	9.000s	14.526us	1	1	100.00
		otbn_zero_state_err_urnd	10.000s	23.443us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	10.318us	1	1	100.00
		otbn_sec_cm	7.000s	9.620us	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	7.000s	9.620us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	9.000s	145.475us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	12.000s	29.375us	1	1	100.00
		otbn_dmem_err	9.000s	14.526us	1	1	100.00
		otbn_zero_state_err_urnd	10.000s	23.443us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	10.318us	1	1	100.00
		otbn_sec_cm	7.000s	9.620us	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	7.000s	9.620us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	1.317m	360.873us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	12.000s	29.375us	1	1	100.00
		otbn_dmem_err	9.000s	14.526us	1	1	100.00
		otbn_zero_state_err_urnd	10.000s	23.443us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	10.318us	1	1	100.00
		otbn_sec_cm	7.000s	9.620us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	7.000s	9.620us	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	9.000s	145.475us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	21.672us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	7.000s	13.003us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	10.000s	145.379us	0	1	0.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	10.000s	145.379us	0	1	0.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	11.000s	59.525us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	7.000s	9.620us	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	7.000s	9.620us	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	13.000s	115.025us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	7.000s	9.620us	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	7.000s	9.620us	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	8.000s	52.427us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	8.000s	52.427us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	7.000s	23.960us	1	1	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	9.000s	145.475us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	9.000s	145.475us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	9.000s	145.475us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	46.000s	789.864us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	9.000s	145.475us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	9.000s	145.475us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	11.000s	58.895us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	9.000s	145.475us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	7.000s	9.620us	0	1	0.00
V2S		TOTAL			18	20	90.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	4.267m	5.460ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	41	95.12

Failure Buckets

• UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 1 failures:

  • Test otbn_rnd_sec_cm has 1 failures.

    • 0.otbn_rnd_sec_cm.90154429576634352502505674633859798497972213080101083231343587634517978882158
      Line 103, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_rnd_sec_cm/latest/run.log

        UVM_FATAL @ 145378819 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
        UVM_INFO @ 145378819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 1 failures:

  • Test otbn_sec_cm has 1 failures.

    • 0.otbn_sec_cm.4657878818263362611263342257900660041282744199573831701539777112898001169923
      Line 87, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 9620035 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 9620035 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
        UVM_ERROR @   9620035 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
        UVM_INFO @   9620035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---